Lines Matching refs:ctrl
364 static void __atl2_vlan_mode(netdev_features_t features, u32 *ctrl)
368 *ctrl |= MAC_CTRL_RMV_VLAN;
371 *ctrl &= ~MAC_CTRL_RMV_VLAN;
379 u32 ctrl;
383 ctrl = ATL2_READ_REG(&adapter->hw, REG_MAC_CTRL);
384 __atl2_vlan_mode(features, &ctrl);
385 ATL2_WRITE_REG(&adapter->hw, REG_MAC_CTRL, ctrl);
1547 u32 ctrl = 0;
1567 atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl);
1568 atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl);
1569 if (ctrl & BMSR_LSTATUS)
1572 if (0 != (ctrl & BMSR_LSTATUS) && 0 != wufc) {
1583 ctrl = 0;
1587 ctrl |= (WOL_MAGIC_EN | WOL_MAGIC_PME_EN);
1590 ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl);
1593 ctrl = MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY;
1595 ctrl |= MAC_CTRL_DUPLX;
1596 ctrl |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1597 ctrl |= (((u32)adapter->hw.preamble_len &
1599 ctrl |= (((u32)(adapter->hw.retry_buf &
1604 ctrl |= MAC_CTRL_BC_EN;
1607 ATL2_WRITE_REG(hw, REG_MAC_CTRL, ctrl);
1610 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);
1611 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
1612 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
1613 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);
1614 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;
1615 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
1621 if (0 == (ctrl&BMSR_LSTATUS) && 0 != (wufc&ATLX_WUFC_LNKC)) {
1623 ctrl |= (WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN);
1624 ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl);
1628 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);
1629 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
1630 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
1631 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);
1632 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;
1633 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
1647 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);
1648 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
1649 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
1650 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);
1651 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;
1652 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);