Cross Reference: /drivers/net/ethernet/broadcom/bnx2x/bnx2x

Lines Matching refs:sig
3914 static inline int bnx2x_check_blocks_with_parity0(u32 sig, int par_num,
3919 	for (i = 0; sig; i++) {
3921 		if (sig & cur_bit) {
3955 			sig &= ~cur_bit;
3962 static inline int bnx2x_check_blocks_with_parity1(u32 sig, int par_num,
3967 	for (i = 0; sig; i++) {
3969 		if (sig & cur_bit) {
4041 			sig &= ~cur_bit;
4048 static inline int bnx2x_check_blocks_with_parity2(u32 sig, int par_num,
4053 	for (i = 0; sig; i++) {
4055 		if (sig & cur_bit) {
4093 			sig &= ~cur_bit;
4100 static inline int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
4105 	for (i = 0; sig; i++) {
4107 		if (sig & cur_bit) {
4135 			sig &= ~cur_bit;
4142 static inline int bnx2x_check_blocks_with_parity4(u32 sig, int par_num,
4147 	for (i = 0; sig; i++) {
4149 		if (sig & cur_bit) {
4162 			sig &= ~cur_bit;
4170 				     u32 *sig)
4172 	if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4173 	    (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4174 	    (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4175 	    (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4176 	    (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4180 			  sig[0] & HW_PRTY_ASSERT_SET_0,
4181 			  sig[1] & HW_PRTY_ASSERT_SET_1,
4182 			  sig[2] & HW_PRTY_ASSERT_SET_2,
4183 			  sig[3] & HW_PRTY_ASSERT_SET_3,
4184 			  sig[4] & HW_PRTY_ASSERT_SET_4);
4189 			sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print);
4191 			sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print);
4193 			sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print);
4195 			sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print);
4197 			sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print);
4219 	attn.sig[0] = REG_RD(bp,
4222 	attn.sig[1] = REG_RD(bp,
4225 	attn.sig[2] = REG_RD(bp,
4228 	attn.sig[3] = REG_RD(bp,
4233 		attn.sig[4] = REG_RD(bp,
4237 	return bnx2x_parity_attn(bp, global, print, attn.sig);
4325 	attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4326 	attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4327 	attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
4328 	attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
4330 		attn.sig[4] =
4333 		attn.sig[4] = 0;
4336 	   attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
4344 			   group_mask->sig[0], group_mask->sig[1],
4345 			   group_mask->sig[2], group_mask->sig[3],
4346 			   group_mask->sig[4]);
4349 					attn.sig[4] & group_mask->sig[4]);
4351 					attn.sig[3] & group_mask->sig[3]);
4353 					attn.sig[1] & group_mask->sig[1]);
4355 					attn.sig[2] & group_mask->sig[2]);
4357 					attn.sig[0] & group_mask->sig[0]);
5117 		/* take care of sig[0]..sig[4] */
5119 			bp->attn_group[index].sig[sindex] =
5128 			bp->attn_group[index].sig[4] = REG_RD(bp,
5131 			bp->attn_group[index].sig[4] = 0;