Cross Reference: /drivers/net/ethernet/chelsio/cxgb3/mc5.c

Lines Matching refs:adap
144 	struct adapter *adap = mc5->adapter;
151 	unsigned int server_base = t3_read_reg(adap, A_MC5_DB_SERVER_INDEX);
159 	dbgi_wr_data3(adap, 0, 0, 0);
161 		if (mc5_write(adap, data_array_base + (i << addr_shift),
166 	dbgi_wr_data3(adap, 0xffffffff, 0xffffffff, 0xff);
169 			t3_write_reg(adap, A_MC5_DB_DBGI_REQ_DATA0,
172 		if (mc5_write(adap, mask_array_base + (i << addr_shift),
182 	struct adapter *adap = mc5->adapter;
184 	t3_write_reg(adap, A_MC5_DB_RSP_LATENCY,
186 	t3_write_reg(adap, A_MC5_DB_PART_ID_INDEX, 2);
192 	t3_write_reg(adap, A_MC5_DB_POPEN_DATA_WR_CMD, IDT_CMD_WRITE);
193 	t3_write_reg(adap, A_MC5_DB_POPEN_MASK_WR_CMD, IDT_CMD_WRITE);
194 	t3_write_reg(adap, A_MC5_DB_AOPEN_SRCH_CMD, IDT_CMD_SEARCH);
195 	t3_write_reg(adap, A_MC5_DB_AOPEN_LRN_CMD, IDT_CMD_LEARN);
196 	t3_write_reg(adap, A_MC5_DB_SYN_SRCH_CMD, IDT_CMD_SEARCH | 0x6000);
197 	t3_write_reg(adap, A_MC5_DB_SYN_LRN_CMD, IDT_CMD_LEARN);
198 	t3_write_reg(adap, A_MC5_DB_ACK_SRCH_CMD, IDT_CMD_SEARCH);
199 	t3_write_reg(adap, A_MC5_DB_ACK_LRN_CMD, IDT_CMD_LEARN);
200 	t3_write_reg(adap, A_MC5_DB_ILOOKUP_CMD, IDT_CMD_SEARCH);
201 	t3_write_reg(adap, A_MC5_DB_ELOOKUP_CMD, IDT_CMD_SEARCH | 0x7000);
202 	t3_write_reg(adap, A_MC5_DB_DATA_WRITE_CMD, IDT_CMD_WRITE);
203 	t3_write_reg(adap, A_MC5_DB_DATA_READ_CMD, IDT_CMD_READ);
206 	t3_write_reg(adap, A_MC5_DB_DBGI_CONFIG, DBGI_MODE_IDT52100);
209 	dbgi_wr_data3(adap, IDT_LAR_MODE144, 0, 0);
210 	if (mc5_write(adap, IDT_LAR_ADR0, IDT_CMD_WRITE))
214 	dbgi_wr_data3(adap, 0xffffffff, 0xffffffff, 0);
215 	if (mc5_write(adap, IDT_SSR0_ADR0, IDT_CMD_WRITE) ||
216 	    mc5_write(adap, IDT_SSR1_ADR0, IDT_CMD_WRITE))
222 			dbgi_wr_data3(adap, 0xfffffff9, 0xffffffff, 0xff);
224 			dbgi_wr_data3(adap, 0xfffffff9, 0xffff8007, 0xff);
226 			dbgi_wr_data3(adap, 0xffffffff, 0xffffffff, 0xff);
228 		if (mc5_write(adap, IDT_GMR_BASE_ADR0 + i, IDT_CMD_WRITE))
233 	dbgi_wr_data3(adap, 1, 0, 0);
234 	if (mc5_write(adap, IDT_SCR_ADR0, IDT_CMD_WRITE))
246 	struct adapter *adap = mc5->adapter;
248 	t3_write_reg(adap, A_MC5_DB_RSP_LATENCY,
249 		     adap->params.rev == 0 ? V_RDLAT(0xd) | V_SRCHLAT(0x11) :
256 	t3_write_reg(adap, A_MC5_DB_POPEN_DATA_WR_CMD, IDT4_CMD_WRITE);
257 	t3_write_reg(adap, A_MC5_DB_POPEN_MASK_WR_CMD, IDT4_CMD_WRITE);
258 	t3_write_reg(adap, A_MC5_DB_AOPEN_SRCH_CMD,
260 	t3_write_reg(adap, A_MC5_DB_SYN_SRCH_CMD, IDT4_CMD_SEARCH144);
261 	t3_write_reg(adap, A_MC5_DB_ACK_SRCH_CMD, IDT4_CMD_SEARCH144 | 0x3800);
262 	t3_write_reg(adap, A_MC5_DB_ILOOKUP_CMD, IDT4_CMD_SEARCH144 | 0x3800);
263 	t3_write_reg(adap, A_MC5_DB_ELOOKUP_CMD, IDT4_CMD_SEARCH144 | 0x800);
264 	t3_write_reg(adap, A_MC5_DB_DATA_WRITE_CMD, IDT4_CMD_WRITE);
265 	t3_write_reg(adap, A_MC5_DB_DATA_READ_CMD, IDT4_CMD_READ);
267 	t3_write_reg(adap, A_MC5_DB_PART_ID_INDEX, 3);
270 	t3_write_reg(adap, A_MC5_DB_DBGI_CONFIG, DBGI_MODE_IDT52100);
273 	dbgi_wr_data3(adap, 0xffffffff, 0xffffffff, 0xff);
275 		if (mc5_write(adap, IDT4_GMR_BASE0 + i, IDT4_CMD_WRITE))
279 		if (mc5_write(adap, IDT4_GMR_BASE2 + i, IDT4_CMD_WRITE))
282 	dbgi_wr_data3(adap, 0xfffffff9, 0xffffffff, 0xff);
283 	if (mc5_write(adap, IDT4_GMR_BASE1, IDT4_CMD_WRITE) ||
284 	    mc5_write(adap, IDT4_GMR_BASE1 + 1, IDT4_CMD_WRITE) ||
285 	    mc5_write(adap, IDT4_GMR_BASE1 + 4, IDT4_CMD_WRITE))
288 	dbgi_wr_data3(adap, 0xfffffff9, 0xffff8007, 0xff);
289 	if (mc5_write(adap, IDT4_GMR_BASE1 + 5, IDT4_CMD_WRITE))
293 	dbgi_wr_data3(adap, 0xf0000000, 0, 0);
294 	if (mc5_write(adap, IDT4_SCR_ADR0, IDT4_CMD_WRITE))
329 	struct adapter *adap = mc5->adapter;
338 	cfg = t3_read_reg(adap, A_MC5_DB_CONFIG) & ~F_TMMODE;
340 	t3_write_reg(adap, A_MC5_DB_CONFIG, cfg);
341 	if (t3_wait_op_done(adap, A_MC5_DB_CONFIG, F_TMRDY, 1, 500, 0)) {
342 		CH_ERR(adap, "TCAM reset timed out\n");
346 	t3_write_reg(adap, A_MC5_DB_ROUTING_TABLE_INDEX, tcam_size - nroutes);
347 	t3_write_reg(adap, A_MC5_DB_FILTER_TABLE,
349 	t3_write_reg(adap, A_MC5_DB_SERVER_INDEX,
355 	t3_write_reg(adap, A_MC5_DB_DBGI_REQ_ADDR1, 0);
356 	t3_write_reg(adap, A_MC5_DB_DBGI_REQ_ADDR2, 0);
368 		CH_ERR(adap, "Unsupported TCAM type %d\n", mc5->part_type);
385 	struct adapter *adap = mc5->adapter;
386 	u32 cause = t3_read_reg(adap, A_MC5_DB_INT_CAUSE);
389 		CH_ALERT(adap, "MC5 parity error\n");
394 		CH_ALERT(adap, "MC5 request queue parity error\n");
399 		CH_ALERT(adap, "MC5 dispatch queue parity error\n");
412 		t3_fatal_err(adap);
414 	t3_write_reg(adap, A_MC5_DB_INT_CAUSE, cause);