319 static int read_eeprom(int ioaddr, int location, struct net_device *dev);
462 #define eepro_reset(ioaddr) outb(RESET_CMD, ioaddr)
465 #define eepro_sel_reset(ioaddr) 	{ \
466 					outb(SEL_RESET_CMD, ioaddr); \
472 #define eepro_dis_int(ioaddr) outb(ALL_MASK, ioaddr + INT_MASK_REG)
475 #define eepro_clear_int(ioaddr) outb(ALL_MASK, ioaddr + STATUS_REG)
478 #define eepro_en_int(ioaddr) outb(ALL_MASK & ~(RX_MASK | TX_MASK), \
479 							ioaddr + INT_MASK_REG)
482 #define eepro_en_intexec(ioaddr) outb(ALL_MASK & ~(EXEC_MASK), ioaddr + INT_MASK_REG)
485 #define eepro_en_rx(ioaddr) outb(RCV_ENABLE_CMD, ioaddr)
488 #define eepro_dis_rx(ioaddr) outb(RCV_DISABLE_CMD, ioaddr)
491 #define eepro_sw2bank0(ioaddr) outb(BANK0_SELECT, ioaddr)
492 #define eepro_sw2bank1(ioaddr) outb(BANK1_SELECT, ioaddr)
493 #define eepro_sw2bank2(ioaddr) outb(BANK2_SELECT, ioaddr)
496 #define eepro_en_intline(ioaddr) outb(inb(ioaddr + REG1) | INT_ENABLE,\
497 				ioaddr + REG1)
500 #define eepro_dis_intline(ioaddr) outb(inb(ioaddr + REG1) & 0x7f, \
501 				ioaddr + REG1);
504 #define eepro_diag(ioaddr) outb(DIAGNOSE_CMD, ioaddr)
507 #define eepro_ack_rx(ioaddr) outb (RX_INT, ioaddr + STATUS_REG)
510 #define eepro_ack_tx(ioaddr) outb (TX_INT, ioaddr + STATUS_REG)
513 #define eepro_complete_selreset(ioaddr) { \
515 						eepro_sel_reset(ioaddr);\
522 						eepro_en_rx(ioaddr);\
608 	int ioaddr = dev->base_addr;
616 		j += read_eeprom(ioaddr, i, dev);
761 	int ioaddr = dev->base_addr;
765 	if (!request_region(ioaddr, EEPRO_IO_EXTENT, DRV_NAME)) {
768 				ioaddr);
775 	id = inb(ioaddr + ID_REG);
786 	if ((inb(ioaddr + ID_REG) & R_ROBIN_BITS) != (counter + 0x40))
799 	station_addr[0] = read_eeprom(ioaddr, 2, dev);
810 		station_addr[0] = read_eeprom(ioaddr, 2, dev);
815 		lp->word[i] = read_eeprom(ioaddr, i, dev);
872 	eepro_reset(ioaddr);
899 	int temp_reg, ioaddr = dev->base_addr;
901 	eepro_sw2bank1(ioaddr); /* be CAREFUL, BANK 1 now */
904 	eepro_en_intline(ioaddr);
907 	eepro_sw2bank0(ioaddr);
910 	eepro_clear_int(ioaddr);
913 	eepro_en_intexec(ioaddr);
916 		eepro_sw2bank1(ioaddr); /* be CAREFUL, BANK 1 now */
918 		temp_reg = inb(ioaddr + INT_NO_REG);
919 		outb((temp_reg & 0xf8) | irqrmap[*irqp], ioaddr + INT_NO_REG);
921 		eepro_sw2bank0(ioaddr); /* Switch back to Bank 0 */
928 			eepro_diag(ioaddr); /* RESET the 82595 */
935 			eepro_clear_int(ioaddr);
939 	eepro_sw2bank1(ioaddr); /* Switch back to Bank 1 */
942 	eepro_dis_intline(ioaddr);
944 	eepro_sw2bank0(ioaddr); /* Switch back to Bank 0 */
947 	eepro_dis_int(ioaddr);
950 	eepro_clear_int(ioaddr);
959 	int i, ioaddr = dev->base_addr;
999 	eepro_sw2bank2(ioaddr); /* be CAREFUL, BANK 2 now */
1000 	temp_reg = inb(ioaddr + lp->eeprom_reg);
1008 		outb(temp_reg & 0xef, ioaddr + lp->eeprom_reg);
1010 		outb(dev->dev_addr[i] , ioaddr + I_ADD_REG0 + i);
1012 	temp_reg = inb(ioaddr + REG1);    /* Setup Transmit Chaining */
1014 		| RCV_Discard_BadFrame, ioaddr + REG1);
1016 	temp_reg = inb(ioaddr + REG2); /* Match broadcast */
1017 	outb(temp_reg | 0x14, ioaddr + REG2);
1019 	temp_reg = inb(ioaddr + REG3);
1020 	outb(temp_reg & 0x3f, ioaddr + REG3); /* clear test mode */
1023 	eepro_sw2bank1(ioaddr); /* be CAREFUL, BANK 1 now */
1026 	temp_reg = inb(ioaddr + INT_NO_REG);
1028 		outb((temp_reg & 0xf8) | irqrmap2[dev->irq], ioaddr + INT_NO_REG);
1029 	else outb((temp_reg & 0xf8) | irqrmap[dev->irq], ioaddr + INT_NO_REG);
1032 	temp_reg = inb(ioaddr + INT_NO_REG);
1034 		outb((temp_reg & 0xf0) | irqrmap2[dev->irq] | 0x08,ioaddr+INT_NO_REG);
1035 	else outb((temp_reg & 0xf8) | irqrmap[dev->irq], ioaddr + INT_NO_REG);
1042 	outb(lp->rcv_lower_limit >> 8, ioaddr + RCV_LOWER_LIMIT_REG);
1043 	outb(lp->rcv_upper_limit >> 8, ioaddr + RCV_UPPER_LIMIT_REG);
1044 	outb(lp->xmt_lower_limit >> 8, ioaddr + lp->xmt_lower_limit_reg);
1045 	outb(lp->xmt_upper_limit >> 8, ioaddr + lp->xmt_upper_limit_reg);
1048 	eepro_en_intline(ioaddr);
1051 	eepro_sw2bank0(ioaddr);
1054 	eepro_en_int(ioaddr);
1057 	eepro_clear_int(ioaddr);
1060 	outw(lp->rcv_lower_limit, ioaddr + RCV_BAR);
1062 	outw(lp->rcv_upper_limit | 0xfe, ioaddr + RCV_STOP);
1065 	outw(lp->xmt_lower_limit, ioaddr + lp->xmt_bar);
1070 	old8 = inb(ioaddr + 8);
1071 	outb(~old8, ioaddr + 8);
1073 	if ((temp_reg = inb(ioaddr + 8)) == old8) {
1080 		outb(old8, ioaddr + 8);
1081 		old9 = inb(ioaddr + 9);
1089 			outb(old9, ioaddr + 9);
1093 				eepro_sw2bank2(ioaddr); /* be CAREFUL, BANK 2 now */
1094 				temp_reg = inb(ioaddr + REG13);
1098 				eepro_sw2bank0(ioaddr); /* be CAREFUL, BANK 0 now */
1107 	eepro_sel_reset(ioaddr);
1115 	eepro_en_rx(ioaddr);
1123 	int ioaddr = dev->base_addr;
1132 	eepro_complete_selreset(ioaddr);
1141 	int ioaddr = dev->base_addr;
1154 	eepro_dis_int(ioaddr);
1178 	eepro_en_int(ioaddr);
1193 	int ioaddr, status, boguscount = 20;
1203 	ioaddr = dev->base_addr;
1205 	while (((status = inb(ioaddr + STATUS_REG)) & (RX_INT|TX_INT)) && (boguscount--))
1212 			eepro_dis_int(ioaddr);
1215 			eepro_ack_rx(ioaddr);
1218 			eepro_en_int(ioaddr);
1225 			eepro_dis_int(ioaddr);
1228 			eepro_ack_tx(ioaddr);
1231 			eepro_en_int(ioaddr);
1245 	int ioaddr = dev->base_addr;
1250 	eepro_sw2bank1(ioaddr); /* Switch back to Bank 1 */
1253 	temp_reg = inb(ioaddr + REG1);
1254 	outb(temp_reg & 0x7f, ioaddr + REG1);
1256 	eepro_sw2bank0(ioaddr); /* Switch back to Bank 0 */
1259 	outb(STOP_RCV_CMD, ioaddr);
1264 	eepro_dis_int(ioaddr);
1267 	eepro_clear_int(ioaddr);
1270 	eepro_reset(ioaddr);
1286 	short ioaddr = dev->base_addr;
1293 		eepro_sw2bank2(ioaddr); /* be CAREFUL, BANK 2 now */
1294 		mode = inb(ioaddr + REG2);
1295 		outb(mode | PRMSC_Mode, ioaddr + REG2);
1296 		mode = inb(ioaddr + REG3);
1297 		outb(mode, ioaddr + REG3); /* writing reg. 3 to complete the update */
1298 		eepro_sw2bank0(ioaddr); /* Return to BANK 0 now */
1303 		eepro_sw2bank2(ioaddr); /* be CAREFUL, BANK 2 now */
1304 		mode = inb(ioaddr + REG2);
1305 		outb(mode & 0xd6, ioaddr + REG2); /* Turn off Multi-IA and PRMSC_Mode bits */
1306 		mode = inb(ioaddr + REG3);
1307 		outb(mode, ioaddr + REG3); /* writing reg. 3 to complete the update */
1308 		eepro_sw2bank0(ioaddr); /* Return to BANK 0 now */
1319 		eepro_dis_int(ioaddr);
1321 		eepro_sw2bank2(ioaddr); /* be CAREFUL, BANK 2 now */
1322 		mode = inb(ioaddr + REG2);
1323 		outb(mode | Multi_IA, ioaddr + REG2);
1324 		mode = inb(ioaddr + REG3);
1325 		outb(mode, ioaddr + REG3); /* writing reg. 3 to complete the update */
1326 		eepro_sw2bank0(ioaddr); /* Return to BANK 0 now */
1327 		outw(lp->tx_end, ioaddr + HOST_ADDRESS_REG);
1328 		outw(MC_SETUP, ioaddr + IO_PORT);
1329 		outw(0, ioaddr + IO_PORT);
1330 		outw(0, ioaddr + IO_PORT);
1331 		outw(6 * (mc_count + 1), ioaddr + IO_PORT);
1335 			outw(*eaddrs++, ioaddr + IO_PORT);
1336 			outw(*eaddrs++, ioaddr + IO_PORT);
1337 			outw(*eaddrs++, ioaddr + IO_PORT);
1341 		outw(eaddrs[0], ioaddr + IO_PORT);
1342 		outw(eaddrs[1], ioaddr + IO_PORT);
1343 		outw(eaddrs[2], ioaddr + IO_PORT);
1344 		outw(lp->tx_end, ioaddr + lp->xmt_bar);
1345 		outb(MC_SETUP, ioaddr);
1354 			outw(lp->tx_last + XMT_CHAIN, ioaddr + HOST_ADDRESS_REG);
1355 			outw(i, ioaddr + IO_PORT);
1356 			outw(lp->tx_last + XMT_COUNT, ioaddr + HOST_ADDRESS_REG);
1357 			status = inw(ioaddr + IO_PORT);
1358 			outw(status | CHAIN_BIT, ioaddr + IO_PORT);
1369 			if (inb(ioaddr + STATUS_REG) & 0x08)
1371 				i = inb(ioaddr);
1372 				outb(0x08, ioaddr + STATUS_REG);
1388 		eepro_en_int(ioaddr);
1391 		eepro_complete_selreset(ioaddr);
1394 		eepro_en_rx(ioaddr);
1405 read_eeprom(int ioaddr, int location, struct net_device *dev)
1410 	short ee_addr = ioaddr + lp->eeprom_reg;
1415 		eepro_sw2bank1(ioaddr);
1416 		outb(0x00, ioaddr + STATUS_REG);
1419 	eepro_sw2bank2(ioaddr);
1446 	eepro_sw2bank0(ioaddr);
1454 	short ioaddr = dev->base_addr;
1486 		outw(last, ioaddr + HOST_ADDRESS_REG);
1487 		outw(XMT_CMD, ioaddr + IO_PORT);
1488 		outw(0, ioaddr + IO_PORT);
1489 		outw(end, ioaddr + IO_PORT);
1490 		outw(length, ioaddr + IO_PORT);
1493 			outsw(ioaddr + IO_PORT, buf, (length + 3) >> 1);
1495 			unsigned short temp = inb(ioaddr + INT_MASK_REG);
1496 			outb(temp | IO_32_BIT, ioaddr + INT_MASK_REG);
1497 			outsl(ioaddr + IO_PORT_32_BIT, buf, (length + 3) >> 2);
1498 			outb(temp & ~(IO_32_BIT), ioaddr + INT_MASK_REG);
1502 		status = inw(ioaddr + IO_PORT);
1505 		outw(last, ioaddr + lp->xmt_bar);
1506 			outb(XMT_CMD, ioaddr);
1514 				outw(lp->tx_last + XMT_CHAIN, ioaddr + HOST_ADDRESS_REG);
1515 				outw(last, ioaddr + IO_PORT);
1518 			outw(lp->tx_last + XMT_COUNT, ioaddr + HOST_ADDRESS_REG);
1519 			status = inw(ioaddr + IO_PORT);
1520 			outw(status | CHAIN_BIT, ioaddr + IO_PORT);
1523 			outb(RESUME_XMT_CMD, ioaddr);
1539 	short ioaddr = dev->base_addr;
1548 	outw(rcv_car, ioaddr + HOST_ADDRESS_REG);
1550 	rcv_event = inw(ioaddr + IO_PORT);
1554 		rcv_status = inw(ioaddr + IO_PORT);
1555 		rcv_next_frame = inw(ioaddr + IO_PORT);
1556 		rcv_size = inw(ioaddr + IO_PORT);
1571 				outw(rcv_next_frame, ioaddr + HOST_ADDRESS_REG);
1578 				insw(ioaddr+IO_PORT, skb_put(skb,rcv_size), (rcv_size + 3) >> 1);
1580 				unsigned short temp = inb(ioaddr + INT_MASK_REG);
1581 				outb(temp | IO_32_BIT, ioaddr + INT_MASK_REG);
1582 				insl(ioaddr+IO_PORT_32_BIT, skb_put(skb,rcv_size),
1584 				outb(temp & ~(IO_32_BIT), ioaddr + INT_MASK_REG);
1618 		outw(rcv_next_frame, ioaddr + HOST_ADDRESS_REG);
1619 		rcv_event = inw(ioaddr + IO_PORT);
1625 	outw(rcv_car - 1, ioaddr + RCV_STOP);
1635 	short ioaddr = dev->base_addr;
1641 		outw(lp->tx_start, ioaddr + HOST_ADDRESS_REG);
1642 		xmt_status = inw(ioaddr+IO_PORT);
1647 		xmt_status = inw(ioaddr+IO_PORT);
1648 		lp->tx_start = inw(ioaddr+IO_PORT);

Indexes created Wed Oct 10 22:18:05 CEST 2012