Lines Matching refs:ctrl_reg
73 u32 ctrl_reg;
75 ctrl_reg = IXGB_CTRL0_RST |
86 IXGB_WRITE_REG_IO(hw, CTRL0, ctrl_reg);
88 IXGB_WRITE_REG(hw, CTRL0, ctrl_reg);
93 ctrl_reg = IXGB_READ_REG(hw, CTRL0);
96 ASSERT(!(ctrl_reg & IXGB_CTRL0_RST));
100 ctrl_reg = /* Enable interrupt from XFP and SerDes */
106 IXGB_WRITE_REG(hw, CTRL1, ctrl_reg);
113 return ctrl_reg;
124 u32 ctrl_reg;
162 ctrl_reg = ixgb_mac_reset(hw);
171 return ctrl_reg & IXGB_CTRL0_RST;
301 u32 ctrl_reg;
313 ctrl_reg = ixgb_mac_reset(hw);
639 u32 ctrl_reg;
646 ctrl_reg = IXGB_READ_REG(hw, CTRL0);
649 ctrl_reg &= ~(IXGB_CTRL0_RPE | IXGB_CTRL0_TPE);
663 ctrl_reg |= (IXGB_CTRL0_CMDC);
669 ctrl_reg |= (IXGB_CTRL0_RPE);
675 ctrl_reg |= (IXGB_CTRL0_TPE);
682 ctrl_reg |= (IXGB_CTRL0_RPE | IXGB_CTRL0_TPE);
693 IXGB_WRITE_REG(hw, CTRL0, ctrl_reg);