Lines Matching refs:hw
1339 * @hw: Pointer to hardware structure.
1353 struct ksz_hw *hw;
1403 * @hw: Hardware structure.
1427 struct ksz_hw hw;
1499 static inline void hw_ack_intr(struct ksz_hw *hw, uint interrupt)
1501 writel(interrupt, hw->io + KS884X_INTERRUPTS_STATUS);
1504 static inline void hw_dis_intr(struct ksz_hw *hw)
1506 hw->intr_blocked = hw->intr_mask;
1507 writel(0, hw->io + KS884X_INTERRUPTS_ENABLE);
1508 hw->intr_set = readl(hw->io + KS884X_INTERRUPTS_ENABLE);
1511 static inline void hw_set_intr(struct ksz_hw *hw, uint interrupt)
1513 hw->intr_set = interrupt;
1514 writel(interrupt, hw->io + KS884X_INTERRUPTS_ENABLE);
1517 static inline void hw_ena_intr(struct ksz_hw *hw)
1519 hw->intr_blocked = 0;
1520 hw_set_intr(hw, hw->intr_mask);
1523 static inline void hw_dis_intr_bit(struct ksz_hw *hw, uint bit)
1525 hw->intr_mask &= ~(bit);
1528 static inline void hw_turn_off_intr(struct ksz_hw *hw, uint interrupt)
1532 read_intr = readl(hw->io + KS884X_INTERRUPTS_ENABLE);
1533 hw->intr_set = read_intr & ~interrupt;
1534 writel(hw->intr_set, hw->io + KS884X_INTERRUPTS_ENABLE);
1535 hw_dis_intr_bit(hw, interrupt);
1540 * @hw: The hardware instance.
1546 static void hw_turn_on_intr(struct ksz_hw *hw, u32 bit)
1548 hw->intr_mask |= bit;
1550 if (!hw->intr_blocked)
1551 hw_set_intr(hw, hw->intr_mask);
1554 static inline void hw_ena_intr_bit(struct ksz_hw *hw, uint interrupt)
1558 read_intr = readl(hw->io + KS884X_INTERRUPTS_ENABLE);
1559 hw->intr_set = read_intr | interrupt;
1560 writel(hw->intr_set, hw->io + KS884X_INTERRUPTS_ENABLE);
1563 static inline void hw_read_intr(struct ksz_hw *hw, uint *status)
1565 *status = readl(hw->io + KS884X_INTERRUPTS_STATUS);
1566 *status = *status & hw->intr_set;
1569 static inline void hw_restore_intr(struct ksz_hw *hw, uint interrupt)
1572 hw_ena_intr(hw);
1583 static uint hw_block_intr(struct ksz_hw *hw)
1587 if (!hw->intr_blocked) {
1588 hw_dis_intr(hw);
1589 interrupt = hw->intr_blocked;
1658 #define HW_DELAY(hw, reg) \
1661 dummy = readw(hw->io + reg); \
1666 * @hw: The hardware instance.
1674 static void sw_r_table(struct ksz_hw *hw, int table, u16 addr, u32 *data)
1681 interrupt = hw_block_intr(hw);
1683 writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET);
1684 HW_DELAY(hw, KS884X_IACR_OFFSET);
1685 *data = readl(hw->io + KS884X_ACC_DATA_0_OFFSET);
1687 hw_restore_intr(hw, interrupt);
1692 * @hw: The hardware instance.
1701 static void sw_w_table_64(struct ksz_hw *hw, int table, u16 addr, u32 data_hi,
1709 interrupt = hw_block_intr(hw);
1711 writel(data_hi, hw->io + KS884X_ACC_DATA_4_OFFSET);
1712 writel(data_lo, hw->io + KS884X_ACC_DATA_0_OFFSET);
1714 writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET);
1715 HW_DELAY(hw, KS884X_IACR_OFFSET);
1717 hw_restore_intr(hw, interrupt);
1722 * @hw: The hardware instance.
1734 static void sw_w_sta_mac_table(struct ksz_hw *hw, u16 addr, u8 *mac_addr,
1755 sw_w_table_64(hw, TABLE_STATIC_MAC, addr, data_hi, data_lo);
1760 * @hw: The hardware instance.
1771 static int sw_r_vlan_table(struct ksz_hw *hw, u16 addr, u16 *vid, u8 *fid,
1776 sw_r_table(hw, TABLE_VLAN, addr, &data);
1789 * @hw: The hardware instance.
1797 static void port_r_mib_cnt(struct ksz_hw *hw, int port, u16 addr, u64 *cnt)
1806 interrupt = hw_block_intr(hw);
1809 writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET);
1810 HW_DELAY(hw, KS884X_IACR_OFFSET);
1813 data = readl(hw->io + KS884X_ACC_DATA_0_OFFSET);
1823 hw_restore_intr(hw, interrupt);
1828 * @hw: The hardware instance.
1835 static void port_r_mib_pkt(struct ksz_hw *hw, int port, u32 *last, u64 *cnt)
1845 interrupt = hw_block_intr(hw);
1850 writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET);
1851 HW_DELAY(hw, KS884X_IACR_OFFSET);
1852 data = readl(hw->io + KS884X_ACC_DATA_0_OFFSET);
1854 hw_restore_intr(hw, interrupt);
1874 * @hw: The hardware instance.
1883 static int port_r_cnt(struct ksz_hw *hw, int port)
1885 struct ksz_port_mib *mib = &hw->port_mib[port];
1889 port_r_mib_cnt(hw, port, mib->cnt_ptr,
1893 if (hw->mib_cnt > PORT_COUNTER_NUM)
1894 port_r_mib_pkt(hw, port, mib->dropped,
1902 * @hw: The hardware instance.
1908 static void port_init_cnt(struct ksz_hw *hw, int port)
1910 struct ksz_port_mib *mib = &hw->port_mib[port];
1915 port_r_mib_cnt(hw, port, mib->cnt_ptr,
1919 if (hw->mib_cnt > PORT_COUNTER_NUM)
1920 port_r_mib_pkt(hw, port, mib->dropped,
1932 * @hw: The hardware instance.
1942 static int port_chk(struct ksz_hw *hw, int port, int offset, u16 bits)
1949 data = readw(hw->io + addr);
1955 * @hw: The hardware instance.
1963 static void port_cfg(struct ksz_hw *hw, int port, int offset, u16 bits,
1971 data = readw(hw->io + addr);
1976 writew(data, hw->io + addr);
1981 * @hw: The hardware instance.
1991 static int port_chk_shift(struct ksz_hw *hw, int port, u32 addr, int shift)
1996 data = readw(hw->io + addr);
2003 * @hw: The hardware instance.
2011 static void port_cfg_shift(struct ksz_hw *hw, int port, u32 addr, int shift,
2017 data = readw(hw->io + addr);
2023 writew(data, hw->io + addr);
2028 * @hw: The hardware instance.
2035 static void port_r8(struct ksz_hw *hw, int port, int offset, u8 *data)
2041 *data = readb(hw->io + addr);
2046 * @hw: The hardware instance.
2053 static void port_r16(struct ksz_hw *hw, int port, int offset, u16 *data)
2059 *data = readw(hw->io + addr);
2064 * @hw: The hardware instance.
2071 static void port_w16(struct ksz_hw *hw, int port, int offset, u16 data)
2077 writew(data, hw->io + addr);
2082 * @hw: The hardware instance.
2091 static int sw_chk(struct ksz_hw *hw, u32 addr, u16 bits)
2095 data = readw(hw->io + addr);
2101 * @hw: The hardware instance.
2108 static void sw_cfg(struct ksz_hw *hw, u32 addr, u16 bits, int set)
2112 data = readw(hw->io + addr);
2117 writew(data, hw->io + addr);
2122 static inline void port_cfg_broad_storm(struct ksz_hw *hw, int p, int set)
2124 port_cfg(hw, p,
2128 static inline int port_chk_broad_storm(struct ksz_hw *hw, int p)
2130 return port_chk(hw, p,
2142 * @hw: The hardware instance.
2147 static void sw_cfg_broad_storm(struct ksz_hw *hw, u8 percent)
2155 data = readw(hw->io + KS8842_SWITCH_CTRL_3_OFFSET);
2158 writew(data, hw->io + KS8842_SWITCH_CTRL_3_OFFSET);
2163 * @hw: The hardware instance.
2168 static void sw_get_broad_storm(struct ksz_hw *hw, u8 *percent)
2173 data = readw(hw->io + KS8842_SWITCH_CTRL_3_OFFSET);
2183 * @hw: The hardware instance.
2188 static void sw_dis_broad_storm(struct ksz_hw *hw, int port)
2190 port_cfg_broad_storm(hw, port, 0);
2195 * @hw: The hardware instance.
2200 static void sw_ena_broad_storm(struct ksz_hw *hw, int port)
2202 sw_cfg_broad_storm(hw, hw->ksz_switch->broad_per);
2203 port_cfg_broad_storm(hw, port, 1);
2208 * @hw: The hardware instance.
2212 static void sw_init_broad_storm(struct ksz_hw *hw)
2216 hw->ksz_switch->broad_per = 1;
2217 sw_cfg_broad_storm(hw, hw->ksz_switch->broad_per);
2219 sw_dis_broad_storm(hw, port);
2220 sw_cfg(hw, KS8842_SWITCH_CTRL_2_OFFSET, MULTICAST_STORM_DISABLE, 1);
2225 * @hw: The hardware instance.
2231 static void hw_cfg_broad_storm(struct ksz_hw *hw, u8 percent)
2236 sw_cfg_broad_storm(hw, percent);
2237 sw_get_broad_storm(hw, &percent);
2238 hw->ksz_switch->broad_per = percent;
2243 * @hw: The hardware instance.
2248 static void sw_dis_prio_rate(struct ksz_hw *hw, int port)
2254 writel(0, hw->io + addr);
2259 * @hw: The hardware instance.
2263 static void sw_init_prio_rate(struct ksz_hw *hw)
2267 struct ksz_switch *sw = hw->ksz_switch;
2274 sw_dis_prio_rate(hw, port);
2280 static inline void port_cfg_back_pressure(struct ksz_hw *hw, int p, int set)
2282 port_cfg(hw, p,
2286 static inline void port_cfg_force_flow_ctrl(struct ksz_hw *hw, int p, int set)
2288 port_cfg(hw, p,
2292 static inline int port_chk_back_pressure(struct ksz_hw *hw, int p)
2294 return port_chk(hw, p,
2298 static inline int port_chk_force_flow_ctrl(struct ksz_hw *hw, int p)
2300 return port_chk(hw, p,
2306 static inline void port_cfg_dis_learn(struct ksz_hw *hw, int p, int set)
2308 port_cfg(hw, p,
2312 static inline void port_cfg_rx(struct ksz_hw *hw, int p, int set)
2314 port_cfg(hw, p,
2318 static inline void port_cfg_tx(struct ksz_hw *hw, int p, int set)
2320 port_cfg(hw, p,
2324 static inline void sw_cfg_fast_aging(struct ksz_hw *hw, int set)
2326 sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET, SWITCH_FAST_AGING, set);
2329 static inline void sw_flush_dyn_mac_table(struct ksz_hw *hw)
2331 if (!(hw->overrides & FAST_AGING)) {
2332 sw_cfg_fast_aging(hw, 1);
2334 sw_cfg_fast_aging(hw, 0);
2340 static inline void port_cfg_ins_tag(struct ksz_hw *hw, int p, int insert)
2342 port_cfg(hw, p,
2346 static inline void port_cfg_rmv_tag(struct ksz_hw *hw, int p, int remove)
2348 port_cfg(hw, p,
2352 static inline int port_chk_ins_tag(struct ksz_hw *hw, int p)
2354 return port_chk(hw, p,
2358 static inline int port_chk_rmv_tag(struct ksz_hw *hw, int p)
2360 return port_chk(hw, p,
2364 static inline void port_cfg_dis_non_vid(struct ksz_hw *hw, int p, int set)
2366 port_cfg(hw, p,
2370 static inline void port_cfg_in_filter(struct ksz_hw *hw, int p, int set)
2372 port_cfg(hw, p,
2376 static inline int port_chk_dis_non_vid(struct ksz_hw *hw, int p)
2378 return port_chk(hw, p,
2382 static inline int port_chk_in_filter(struct ksz_hw *hw, int p)
2384 return port_chk(hw, p,
2390 static inline void port_cfg_mirror_sniffer(struct ksz_hw *hw, int p, int set)
2392 port_cfg(hw, p,
2396 static inline void port_cfg_mirror_rx(struct ksz_hw *hw, int p, int set)
2398 port_cfg(hw, p,
2402 static inline void port_cfg_mirror_tx(struct ksz_hw *hw, int p, int set)
2404 port_cfg(hw, p,
2408 static inline void sw_cfg_mirror_rx_tx(struct ksz_hw *hw, int set)
2410 sw_cfg(hw, KS8842_SWITCH_CTRL_2_OFFSET, SWITCH_MIRROR_RX_TX, set);
2413 static void sw_init_mirror(struct ksz_hw *hw)
2418 port_cfg_mirror_sniffer(hw, port, 0);
2419 port_cfg_mirror_rx(hw, port, 0);
2420 port_cfg_mirror_tx(hw, port, 0);
2422 sw_cfg_mirror_rx_tx(hw, 0);
2425 static inline void sw_cfg_unk_def_deliver(struct ksz_hw *hw, int set)
2427 sw_cfg(hw, KS8842_SWITCH_CTRL_7_OFFSET,
2431 static inline int sw_cfg_chk_unk_def_deliver(struct ksz_hw *hw)
2433 return sw_chk(hw, KS8842_SWITCH_CTRL_7_OFFSET,
2437 static inline void sw_cfg_unk_def_port(struct ksz_hw *hw, int port, int set)
2439 port_cfg_shift(hw, port, KS8842_SWITCH_CTRL_7_OFFSET, 0, set);
2442 static inline int sw_chk_unk_def_port(struct ksz_hw *hw, int port)
2444 return port_chk_shift(hw, port, KS8842_SWITCH_CTRL_7_OFFSET, 0);
2449 static inline void port_cfg_diffserv(struct ksz_hw *hw, int p, int set)
2451 port_cfg(hw, p,
2455 static inline void port_cfg_802_1p(struct ksz_hw *hw, int p, int set)
2457 port_cfg(hw, p,
2461 static inline void port_cfg_replace_vid(struct ksz_hw *hw, int p, int set)
2463 port_cfg(hw, p,
2467 static inline void port_cfg_prio(struct ksz_hw *hw, int p, int set)
2469 port_cfg(hw, p,
2473 static inline int port_chk_diffserv(struct ksz_hw *hw, int p)
2475 return port_chk(hw, p,
2479 static inline int port_chk_802_1p(struct ksz_hw *hw, int p)
2481 return port_chk(hw, p,
2485 static inline int port_chk_replace_vid(struct ksz_hw *hw, int p)
2487 return port_chk(hw, p,
2491 static inline int port_chk_prio(struct ksz_hw *hw, int p)
2493 return port_chk(hw, p,
2499 * @hw: The hardware instance.
2504 static void sw_dis_diffserv(struct ksz_hw *hw, int port)
2506 port_cfg_diffserv(hw, port, 0);
2511 * @hw: The hardware instance.
2516 static void sw_dis_802_1p(struct ksz_hw *hw, int port)
2518 port_cfg_802_1p(hw, port, 0);
2523 * @hw: The hardware instance.
2527 static void sw_cfg_replace_null_vid(struct ksz_hw *hw, int set)
2529 sw_cfg(hw, KS8842_SWITCH_CTRL_3_OFFSET, SWITCH_REPLACE_NULL_VID, set);
2534 * @hw: The hardware instance.
2543 static void sw_cfg_replace_vid(struct ksz_hw *hw, int port, int set)
2545 port_cfg_replace_vid(hw, port, set);
2550 * @hw: The hardware instance.
2556 static void sw_cfg_port_based(struct ksz_hw *hw, int port, u8 prio)
2563 hw->ksz_switch->port_cfg[port].port_prio = prio;
2565 port_r16(hw, port, KS8842_PORT_CTRL_1_OFFSET, &data);
2568 port_w16(hw, port, KS8842_PORT_CTRL_1_OFFSET, data);
2573 * @hw: The hardware instance.
2579 static void sw_dis_multi_queue(struct ksz_hw *hw, int port)
2581 port_cfg_prio(hw, port, 0);
2586 * @hw: The hardware instance.
2590 static void sw_init_prio(struct ksz_hw *hw)
2594 struct ksz_switch *sw = hw->ksz_switch;
2618 sw_dis_multi_queue(hw, port);
2619 sw_dis_diffserv(hw, port);
2620 sw_dis_802_1p(hw, port);
2621 sw_cfg_replace_vid(hw, port, 0);
2624 sw_cfg_port_based(hw, port, sw->port_cfg[port].port_prio);
2626 sw_cfg_replace_null_vid(hw, 0);
2631 * @hw: The hardware instance.
2637 static void port_get_def_vid(struct ksz_hw *hw, int port, u16 *vid)
2643 *vid = readw(hw->io + addr);
2648 * @hw: The hardware instance.
2652 static void sw_init_vlan(struct ksz_hw *hw)
2656 struct ksz_switch *sw = hw->ksz_switch;
2660 sw_r_vlan_table(hw, entry,
2667 port_get_def_vid(hw, port, &sw->port_cfg[port].vid);
2674 * @hw: The hardware instance.
2680 static void sw_cfg_port_base_vlan(struct ksz_hw *hw, int port, u8 member)
2688 data = readb(hw->io + addr);
2691 writeb(data, hw->io + addr);
2693 hw->ksz_switch->port_cfg[port].member = member;
2698 * @hw: The hardware instance.
2703 static inline void sw_get_addr(struct ksz_hw *hw, u8 *mac_addr)
2708 mac_addr[i] = readb(hw->io + KS8842_MAC_ADDR_0_OFFSET + i);
2709 mac_addr[1 + i] = readb(hw->io + KS8842_MAC_ADDR_1_OFFSET + i);
2715 * @hw: The hardware instance.
2720 static void sw_set_addr(struct ksz_hw *hw, u8 *mac_addr)
2725 writeb(mac_addr[i], hw->io + KS8842_MAC_ADDR_0_OFFSET + i);
2726 writeb(mac_addr[1 + i], hw->io + KS8842_MAC_ADDR_1_OFFSET + i);
2732 * @hw: The hardware instance.
2736 static void sw_set_global_ctrl(struct ksz_hw *hw)
2741 data = readw(hw->io + KS8842_SWITCH_CTRL_3_OFFSET);
2743 writew(data, hw->io + KS8842_SWITCH_CTRL_3_OFFSET);
2745 data = readw(hw->io + KS8842_SWITCH_CTRL_1_OFFSET);
2754 if (hw->overrides & FAST_AGING)
2758 writew(data, hw->io + KS8842_SWITCH_CTRL_1_OFFSET);
2760 data = readw(hw->io + KS8842_SWITCH_CTRL_2_OFFSET);
2764 writew(data, hw->io + KS8842_SWITCH_CTRL_2_OFFSET);
2778 * @hw: The hardware instance.
2784 static void port_set_stp_state(struct ksz_hw *hw, int port, int state)
2788 port_r16(hw, port, KS8842_PORT_CTRL_2_OFFSET, &data);
2825 port_w16(hw, port, KS8842_PORT_CTRL_2_OFFSET, data);
2826 hw->ksz_switch->port_cfg[port].stp_state = state;
2836 * @hw: The hardware instance.
2840 static void sw_clr_sta_mac_table(struct ksz_hw *hw)
2846 entry = &hw->ksz_switch->mac_table[i];
2847 sw_w_sta_mac_table(hw, i,
2856 * @hw: The hardware instance.
2860 static void sw_init_stp(struct ksz_hw *hw)
2864 entry = &hw->ksz_switch->mac_table[STP_ENTRY];
2874 sw_w_sta_mac_table(hw, STP_ENTRY,
2882 * @hw: The hardware instance.
2886 static void sw_block_addr(struct ksz_hw *hw)
2892 entry = &hw->ksz_switch->mac_table[i];
2894 sw_w_sta_mac_table(hw, i,
2910 static inline void hw_r_phy_ctrl(struct ksz_hw *hw, int phy, u16 *data)
2912 *data = readw(hw->io + phy + KS884X_PHY_CTRL_OFFSET);
2915 static inline void hw_w_phy_ctrl(struct ksz_hw *hw, int phy, u16 data)
2917 writew(data, hw->io + phy + KS884X_PHY_CTRL_OFFSET);
2920 static inline void hw_r_phy_link_stat(struct ksz_hw *hw, int phy, u16 *data)
2922 *data = readw(hw->io + phy + KS884X_PHY_STATUS_OFFSET);
2925 static inline void hw_r_phy_auto_neg(struct ksz_hw *hw, int phy, u16 *data)
2927 *data = readw(hw->io + phy + KS884X_PHY_AUTO_NEG_OFFSET);
2930 static inline void hw_w_phy_auto_neg(struct ksz_hw *hw, int phy, u16 data)
2932 writew(data, hw->io + phy + KS884X_PHY_AUTO_NEG_OFFSET);
2935 static inline void hw_r_phy_rem_cap(struct ksz_hw *hw, int phy, u16 *data)
2937 *data = readw(hw->io + phy + KS884X_PHY_REMOTE_CAP_OFFSET);
2940 static inline void hw_r_phy_crossover(struct ksz_hw *hw, int phy, u16 *data)
2942 *data = readw(hw->io + phy + KS884X_PHY_CTRL_OFFSET);
2945 static inline void hw_w_phy_crossover(struct ksz_hw *hw, int phy, u16 data)
2947 writew(data, hw->io + phy + KS884X_PHY_CTRL_OFFSET);
2950 static inline void hw_r_phy_polarity(struct ksz_hw *hw, int phy, u16 *data)
2952 *data = readw(hw->io + phy + KS884X_PHY_PHY_CTRL_OFFSET);
2955 static inline void hw_w_phy_polarity(struct ksz_hw *hw, int phy, u16 data)
2957 writew(data, hw->io + phy + KS884X_PHY_PHY_CTRL_OFFSET);
2960 static inline void hw_r_phy_link_md(struct ksz_hw *hw, int phy, u16 *data)
2962 *data = readw(hw->io + phy + KS884X_PHY_LINK_MD_OFFSET);
2965 static inline void hw_w_phy_link_md(struct ksz_hw *hw, int phy, u16 data)
2967 writew(data, hw->io + phy + KS884X_PHY_LINK_MD_OFFSET);
2972 * @hw: The hardware instance.
2979 static void hw_r_phy(struct ksz_hw *hw, int port, u16 reg, u16 *val)
2984 *val = readw(hw->io + phy);
2989 * @hw: The hardware instance.
2996 static void hw_w_phy(struct ksz_hw *hw, int port, u16 reg, u16 val)
3001 writew(val, hw->io + phy);
3020 static inline void drop_gpio(struct ksz_hw *hw, u8 gpio)
3024 data = readw(hw->io + KS884X_EEPROM_CTRL_OFFSET);
3026 writew(data, hw->io + KS884X_EEPROM_CTRL_OFFSET);
3029 static inline void raise_gpio(struct ksz_hw *hw, u8 gpio)
3033 data = readw(hw->io + KS884X_EEPROM_CTRL_OFFSET);
3035 writew(data, hw->io + KS884X_EEPROM_CTRL_OFFSET);
3038 static inline u8 state_gpio(struct ksz_hw *hw, u8 gpio)
3042 data = readw(hw->io + KS884X_EEPROM_CTRL_OFFSET);
3046 static void eeprom_clk(struct ksz_hw *hw)
3048 raise_gpio(hw, EEPROM_SERIAL_CLOCK);
3050 drop_gpio(hw, EEPROM_SERIAL_CLOCK);
3054 static u16 spi_r(struct ksz_hw *hw)
3060 raise_gpio(hw, EEPROM_SERIAL_CLOCK);
3063 temp |= (state_gpio(hw, EEPROM_DATA_IN)) ? 1 << i : 0;
3065 drop_gpio(hw, EEPROM_SERIAL_CLOCK);
3071 static void spi_w(struct ksz_hw *hw, u16 data)
3076 (data & (0x01 << i)) ? raise_gpio(hw, EEPROM_DATA_OUT) :
3077 drop_gpio(hw, EEPROM_DATA_OUT);
3078 eeprom_clk(hw);
3082 static void spi_reg(struct ksz_hw *hw, u8 data, u8 reg)
3087 raise_gpio(hw, EEPROM_DATA_OUT);
3088 eeprom_clk(hw);
3092 (data & (0x01 << i)) ? raise_gpio(hw, EEPROM_DATA_OUT) :
3093 drop_gpio(hw, EEPROM_DATA_OUT);
3094 eeprom_clk(hw);
3099 (reg & (0x01 << i)) ? raise_gpio(hw, EEPROM_DATA_OUT) :
3100 drop_gpio(hw, EEPROM_DATA_OUT);
3101 eeprom_clk(hw);
3118 * @hw: The hardware instance.
3125 static u16 eeprom_read(struct ksz_hw *hw, u8 reg)
3129 raise_gpio(hw, EEPROM_ACCESS_ENABLE | EEPROM_CHIP_SELECT);
3131 spi_reg(hw, AT93C_READ, reg);
3132 data = spi_r(hw);
3134 drop_gpio(hw, EEPROM_ACCESS_ENABLE | EEPROM_CHIP_SELECT);
3141 * @hw: The hardware instance.
3147 static void eeprom_write(struct ksz_hw *hw, u8 reg, u16 data)
3151 raise_gpio(hw, EEPROM_ACCESS_ENABLE | EEPROM_CHIP_SELECT);
3154 spi_reg(hw, AT93C_CODE, AT93C_WR_ON);
3155 drop_gpio(hw, EEPROM_CHIP_SELECT);
3159 raise_gpio(hw, EEPROM_CHIP_SELECT);
3160 spi_reg(hw, AT93C_ERASE, reg);
3161 drop_gpio(hw, EEPROM_CHIP_SELECT);
3165 raise_gpio(hw, EEPROM_CHIP_SELECT);
3170 } while (!state_gpio(hw, EEPROM_DATA_IN) && --timeout);
3171 drop_gpio(hw, EEPROM_CHIP_SELECT);
3175 raise_gpio(hw, EEPROM_CHIP_SELECT);
3176 spi_reg(hw, AT93C_WRITE, reg);
3177 spi_w(hw, data);
3178 drop_gpio(hw, EEPROM_CHIP_SELECT);
3182 raise_gpio(hw, EEPROM_CHIP_SELECT);
3187 } while (!state_gpio(hw, EEPROM_DATA_IN) && --timeout);
3188 drop_gpio(hw, EEPROM_CHIP_SELECT);
3192 raise_gpio(hw, EEPROM_CHIP_SELECT);
3193 spi_reg(hw, AT93C_CODE, AT93C_WR_OFF);
3195 drop_gpio(hw, EEPROM_ACCESS_ENABLE | EEPROM_CHIP_SELECT);
3218 static void set_flow_ctrl(struct ksz_hw *hw, int rx, int tx)
3223 rx_cfg = hw->rx_cfg;
3224 tx_cfg = hw->tx_cfg;
3226 hw->rx_cfg |= DMA_RX_FLOW_ENABLE;
3228 hw->rx_cfg &= ~DMA_RX_FLOW_ENABLE;
3230 hw->tx_cfg |= DMA_TX_FLOW_ENABLE;
3232 hw->tx_cfg &= ~DMA_TX_FLOW_ENABLE;
3233 if (hw->enabled) {
3234 if (rx_cfg != hw->rx_cfg)
3235 writel(hw->rx_cfg, hw->io + KS_DMA_RX_CTRL);
3236 if (tx_cfg != hw->tx_cfg)
3237 writel(hw->tx_cfg, hw->io + KS_DMA_TX_CTRL);
3241 static void determine_flow_ctrl(struct ksz_hw *hw, struct ksz_port *port,
3247 if (hw->overrides & PAUSE_FLOW_CTRL)
3265 if (!hw->ksz_switch)
3266 set_flow_ctrl(hw, rx, tx);
3269 static inline void port_cfg_change(struct ksz_hw *hw, struct ksz_port *port,
3272 if ((hw->features & HALF_DUPLEX_SIGNAL_BUG) &&
3273 !(hw->overrides & PAUSE_FLOW_CTRL)) {
3274 u32 cfg = hw->tx_cfg;
3278 hw->tx_cfg &= ~DMA_TX_FLOW_ENABLE;
3279 if (hw->enabled && cfg != hw->tx_cfg)
3280 writel(hw->tx_cfg, hw->io + KS_DMA_TX_CTRL);
3296 struct ksz_hw *hw = port->hw;
3305 interrupt = hw_block_intr(hw);
3308 info = &hw->port_info[p];
3309 port_r16(hw, p, KS884X_PORT_CTRL_4_OFFSET, &data);
3310 port_r16(hw, p, KS884X_PORT_STATUS_OFFSET, &status);
3341 hw_r_phy(hw, p, KS884X_PHY_AUTO_NEG_OFFSET,
3343 hw_r_phy(hw, p, KS884X_PHY_REMOTE_CAP_OFFSET,
3345 determine_flow_ctrl(hw, port, data, status);
3346 if (hw->ksz_switch) {
3347 port_cfg_back_pressure(hw, p,
3351 port_cfg_change(hw, port, info, status);
3359 hw->port_mib[p].link_down = 1;
3363 hw->port_mib[p].state = (u8) info->state;
3369 hw_restore_intr(hw, interrupt);
3383 struct ksz_hw *hw = port->hw;
3391 info = &hw->port_info[p];
3393 port_r16(hw, p, KS884X_PORT_CTRL_4_OFFSET, &data);
3394 port_r8(hw, p, KS884X_PORT_STATUS_OFFSET, &status);
3423 port_w16(hw, p, KS884X_PORT_CTRL_4_OFFSET, data);
3436 struct ksz_hw *hw = port->hw;
3444 hw_r_phy_ctrl(hw, phy, &data);
3456 hw_w_phy_ctrl(hw, phy, data);
3462 struct ksz_hw *hw = port->hw;
3467 port_cfg(hw, p,
3477 * @hw: The hardware instance.
3483 static int hw_chk_wol_pme_status(struct ksz_hw *hw)
3485 struct dev_info *hw_priv = container_of(hw, struct dev_info, hw);
3497 * @hw: The hardware instance.
3501 static void hw_clr_wol_pme_status(struct ksz_hw *hw)
3503 struct dev_info *hw_priv = container_of(hw, struct dev_info, hw);
3518 * @hw: The hardware instance.
3523 static void hw_cfg_wol_pme(struct ksz_hw *hw, int set)
3525 struct dev_info *hw_priv = container_of(hw, struct dev_info, hw);
3542 * @hw: The hardware instance.
3548 static void hw_cfg_wol(struct ksz_hw *hw, u16 frame, int set)
3552 data = readw(hw->io + KS8841_WOL_CTRL_OFFSET);
3557 writew(data, hw->io + KS8841_WOL_CTRL_OFFSET);
3562 * @hw: The hardware instance.
3571 static void hw_set_wol_frame(struct ksz_hw *hw, int i, uint mask_size,
3588 writel(0, hw->io + KS8841_WOL_FRAME_BYTE0_OFFSET + i);
3589 writel(0, hw->io + KS8841_WOL_FRAME_BYTE2_OFFSET + i);
3601 writeb(val, hw->io + KS8841_WOL_FRAME_BYTE0_OFFSET + i
3614 writeb(bits, hw->io + KS8841_WOL_FRAME_BYTE0_OFFSET + i + len -
3618 writel(crc, hw->io + KS8841_WOL_FRAME_CRC_OFFSET + i);
3623 * @hw: The hardware instance.
3628 static void hw_add_wol_arp(struct ksz_hw *hw, const u8 *ip_addr)
3642 hw_set_wol_frame(hw, 3, 6, mask, 42, pattern);
3647 * @hw: The hardware instance.
3651 static void hw_add_wol_bcast(struct ksz_hw *hw)
3656 hw_set_wol_frame(hw, 2, 1, mask, ETH_ALEN, pattern);
3661 * @hw: The hardware instance.
3669 static void hw_add_wol_mcast(struct ksz_hw *hw)
3674 memcpy(&pattern[3], &hw->override_addr[3], 3);
3675 hw_set_wol_frame(hw, 1, 1, mask, 6, pattern);
3680 * @hw: The hardware instance.
3687 static void hw_add_wol_ucast(struct ksz_hw *hw)
3691 hw_set_wol_frame(hw, 0, 1, mask, ETH_ALEN, hw->override_addr);
3696 * @hw: The hardware instance.
3702 static void hw_enable_wol(struct ksz_hw *hw, u32 wol_enable, const u8 *net_addr)
3704 hw_cfg_wol(hw, KS8841_WOL_MAGIC_ENABLE, (wol_enable & WAKE_MAGIC));
3705 hw_cfg_wol(hw, KS8841_WOL_FRAME0_ENABLE, (wol_enable & WAKE_UCAST));
3706 hw_add_wol_ucast(hw);
3707 hw_cfg_wol(hw, KS8841_WOL_FRAME1_ENABLE, (wol_enable & WAKE_MCAST));
3708 hw_add_wol_mcast(hw);
3709 hw_cfg_wol(hw, KS8841_WOL_FRAME2_ENABLE, (wol_enable & WAKE_BCAST));
3710 hw_cfg_wol(hw, KS8841_WOL_FRAME3_ENABLE, (wol_enable & WAKE_ARP));
3711 hw_add_wol_arp(hw, net_addr);
3716 * @hw: The hardware instance.
3723 static int hw_init(struct ksz_hw *hw)
3730 writew(BUS_SPEED_125_MHZ, hw->io + KS884X_BUS_CTRL_OFFSET);
3733 data = readw(hw->io + KS884X_CHIP_ID_OFFSET);
3746 hw->features |= SMALL_PACKET_TX_BUG;
3748 hw->features |= HALF_DUPLEX_SIGNAL_BUG;
3755 * @hw: The hardware instance.
3759 static void hw_reset(struct ksz_hw *hw)
3761 writew(GLOBAL_SOFTWARE_RESET, hw->io + KS884X_GLOBAL_CTRL_OFFSET);
3767 writew(0, hw->io + KS884X_GLOBAL_CTRL_OFFSET);
3772 * @hw: The hardware instance.
3776 static void hw_setup(struct ksz_hw *hw)
3782 data = readw(hw->io + KS8842_SWITCH_CTRL_5_OFFSET);
3785 writew(data, hw->io + KS8842_SWITCH_CTRL_5_OFFSET);
3789 hw->tx_cfg = (DMA_TX_PAD_ENABLE | DMA_TX_CRC_ENABLE |
3793 hw->rx_cfg = (DMA_RX_BROADCAST | DMA_RX_UNICAST |
3795 hw->rx_cfg |= KS884X_DMA_RX_MULTICAST;
3798 hw->rx_cfg |= (DMA_RX_CSUM_TCP | DMA_RX_CSUM_IP);
3800 if (hw->all_multi)
3801 hw->rx_cfg |= DMA_RX_ALL_MULTICAST;
3802 if (hw->promiscuous)
3803 hw->rx_cfg |= DMA_RX_PROMISCUOUS;
3808 * @hw: The hardware instance.
3812 static void hw_setup_intr(struct ksz_hw *hw)
3814 hw->intr_mask = KS884X_INT_MASK | KS884X_INT_RX_OVERRUN;
3869 * @hw: The hardware instance.
3875 static void hw_set_desc_base(struct ksz_hw *hw, u32 tx_addr, u32 rx_addr)
3878 writel(tx_addr, hw->io + KS_DMA_TX_ADDR);
3879 writel(rx_addr, hw->io + KS_DMA_RX_ADDR);
3889 static inline void hw_resume_rx(struct ksz_hw *hw)
3891 writel(DMA_START, hw->io + KS_DMA_RX_START);
3896 * @hw: The hardware instance.
3900 static void hw_start_rx(struct ksz_hw *hw)
3902 writel(hw->rx_cfg, hw->io + KS_DMA_RX_CTRL);
3905 hw->intr_mask |= KS884X_INT_RX_STOPPED;
3907 writel(DMA_START, hw->io + KS_DMA_RX_START);
3908 hw_ack_intr(hw, KS884X_INT_RX_STOPPED);
3909 hw->rx_stop++;
3912 if (0 == hw->rx_stop)
3913 hw->rx_stop = 2;
3918 * @hw: The hardware instance.
3922 static void hw_stop_rx(struct ksz_hw *hw)
3924 hw->rx_stop = 0;
3925 hw_turn_off_intr(hw, KS884X_INT_RX_STOPPED);
3926 writel((hw->rx_cfg & ~DMA_RX_ENABLE), hw->io + KS_DMA_RX_CTRL);
3931 * @hw: The hardware instance.
3935 static void hw_start_tx(struct ksz_hw *hw)
3937 writel(hw->tx_cfg, hw->io + KS_DMA_TX_CTRL);
3942 * @hw: The hardware instance.
3946 static void hw_stop_tx(struct ksz_hw *hw)
3948 writel((hw->tx_cfg & ~DMA_TX_ENABLE), hw->io + KS_DMA_TX_CTRL);
3953 * @hw: The hardware instance.
3957 static void hw_disable(struct ksz_hw *hw)
3959 hw_stop_rx(hw);
3960 hw_stop_tx(hw);
3961 hw->enabled = 0;
3966 * @hw: The hardware instance.
3970 static void hw_enable(struct ksz_hw *hw)
3972 hw_start_tx(hw);
3973 hw_start_rx(hw);
3974 hw->enabled = 1;
3979 * @hw: The hardware instance.
3987 static int hw_alloc_pkt(struct ksz_hw *hw, int length, int physical)
3990 if (hw->tx_desc_info.avail <= 1)
3994 get_tx_pkt(&hw->tx_desc_info, &hw->tx_desc_info.cur);
3995 hw->tx_desc_info.cur->sw.buf.tx.first_seg = 1;
3998 ++hw->tx_int_cnt;
3999 hw->tx_size += length;
4002 if (hw->tx_size >= MAX_TX_HELD_SIZE)
4003 hw->tx_int_cnt = hw->tx_int_mask + 1;
4005 if (physical > hw->tx_desc_info.avail)
4008 return hw->tx_desc_info.avail;
4013 * @hw: The hardware instance.
4017 static void hw_send_pkt(struct ksz_hw *hw)
4019 struct ksz_desc *cur = hw->tx_desc_info.cur;
4024 if (hw->tx_int_cnt > hw->tx_int_mask) {
4026 hw->tx_int_cnt = 0;
4027 hw->tx_size = 0;
4031 cur->sw.buf.tx.dest_port = hw->dst_ports;
4035 writel(0, hw->io + KS_DMA_TX_START);
4048 * @hw: The hardware instance.
4053 static void hw_set_addr(struct ksz_hw *hw)
4058 writeb(hw->override_addr[MAC_ADDR_ORDER(i)],
4059 hw->io + KS884X_ADDR_0_OFFSET + i);
4061 sw_set_addr(hw, hw->override_addr);
4066 * @hw: The hardware instance.
4070 static void hw_read_addr(struct ksz_hw *hw)
4075 hw->perm_addr[MAC_ADDR_ORDER(i)] = readb(hw->io +
4078 if (!hw->mac_override) {
4079 memcpy(hw->override_addr, hw->perm_addr, ETH_ALEN);
4080 if (empty_addr(hw->override_addr)) {
4081 memcpy(hw->perm_addr, DEFAULT_MAC_ADDRESS, ETH_ALEN);
4082 memcpy(hw->override_addr, DEFAULT_MAC_ADDRESS,
4084 hw->override_addr[5] += hw->id;
4085 hw_set_addr(hw);
4090 static void hw_ena_add_addr(struct ksz_hw *hw, int index, u8 *mac_addr)
4109 writel(mac_addr_lo, hw->io + index + KS_ADD_ADDR_0_LO);
4110 writel(mac_addr_hi, hw->io + index + KS_ADD_ADDR_0_HI);
4113 static void hw_set_add_addr(struct ksz_hw *hw)
4118 if (empty_addr(hw->address[i]))
4119 writel(0, hw->io + ADD_ADDR_INCR * i +
4122 hw_ena_add_addr(hw, i, hw->address[i]);
4126 static int hw_add_addr(struct ksz_hw *hw, u8 *mac_addr)
4131 if (!memcmp(hw->override_addr, mac_addr, ETH_ALEN))
4133 for (i = 0; i < hw->addr_list_size; i++) {
4134 if (!memcmp(hw->address[i], mac_addr, ETH_ALEN))
4136 if (ADDITIONAL_ENTRIES == j && empty_addr(hw->address[i]))
4140 memcpy(hw->address[j], mac_addr, ETH_ALEN);
4141 hw_ena_add_addr(hw, j, hw->address[j]);
4147 static int hw_del_addr(struct ksz_hw *hw, u8 *mac_addr)
4151 for (i = 0; i < hw->addr_list_size; i++) {
4152 if (!memcmp(hw->address[i], mac_addr, ETH_ALEN)) {
4153 memset(hw->address[i], 0, ETH_ALEN);
4154 writel(0, hw->io + ADD_ADDR_INCR * i +
4164 * @hw: The hardware instance.
4168 static void hw_clr_multicast(struct ksz_hw *hw)
4173 hw->multi_bits[i] = 0;
4175 writeb(0, hw->io + KS884X_MULTICAST_0_OFFSET + i);
4181 * @hw: The hardware instance.
4186 static void hw_set_grp_addr(struct ksz_hw *hw)
4193 memset(hw->multi_bits, 0, sizeof(u8) * HW_MULTICAST_SIZE);
4195 for (i = 0; i < hw->multi_list_size; i++) {
4196 position = (ether_crc(6, hw->multi_list[i]) >> 26) & 0x3f;
4199 hw->multi_bits[index] |= (u8) value;
4203 writeb(hw->multi_bits[i], hw->io + KS884X_MULTICAST_0_OFFSET +
4209 * @hw: The hardware instance.
4214 static void hw_set_multicast(struct ksz_hw *hw, u8 multicast)
4217 hw_stop_rx(hw);
4220 hw->rx_cfg |= DMA_RX_ALL_MULTICAST;
4222 hw->rx_cfg &= ~DMA_RX_ALL_MULTICAST;
4224 if (hw->enabled)
4225 hw_start_rx(hw);
4230 * @hw: The hardware instance.
4235 static void hw_set_promiscuous(struct ksz_hw *hw, u8 prom)
4238 hw_stop_rx(hw);
4241 hw->rx_cfg |= DMA_RX_PROMISCUOUS;
4243 hw->rx_cfg &= ~DMA_RX_PROMISCUOUS;
4245 if (hw->enabled)
4246 hw_start_rx(hw);
4251 * @hw: The hardware instance.
4256 static void sw_enable(struct ksz_hw *hw, int enable)
4261 if (hw->dev_count > 1) {
4263 sw_cfg_port_base_vlan(hw, port,
4265 port_set_stp_state(hw, port, STP_STATE_DISABLED);
4267 sw_cfg_port_base_vlan(hw, port, PORT_MASK);
4268 port_set_stp_state(hw, port, STP_STATE_FORWARDING);
4271 if (hw->dev_count > 1)
4272 port_set_stp_state(hw, SWITCH_PORT_NUM, STP_STATE_SIMPLE);
4274 port_set_stp_state(hw, SWITCH_PORT_NUM, STP_STATE_FORWARDING);
4278 writew(enable, hw->io + KS884X_CHIP_ID_OFFSET);
4283 * @hw: The hardware instance.
4287 static void sw_setup(struct ksz_hw *hw)
4291 sw_set_global_ctrl(hw);
4294 sw_init_broad_storm(hw);
4295 hw_cfg_broad_storm(hw, BROADCAST_STORM_PROTECTION_RATE);
4297 sw_ena_broad_storm(hw, port);
4299 sw_init_prio(hw);
4301 sw_init_mirror(hw);
4303 sw_init_prio_rate(hw);
4305 sw_init_vlan(hw);
4307 if (hw->features & STP_SUPPORT)
4308 sw_init_stp(hw);
4309 if (!sw_chk(hw, KS8842_SWITCH_CTRL_1_OFFSET,
4311 hw->overrides |= PAUSE_FLOW_CTRL;
4312 sw_enable(hw, 1);
4402 struct ksz_hw *hw = &adapter->hw;
4407 hw->rx_desc_info.size * hw->rx_desc_info.alloc +
4408 hw->tx_desc_info.size * hw->tx_desc_info.alloc +
4429 hw->rx_desc_info.ring_virt = (struct ksz_hw_desc *)
4431 hw->rx_desc_info.ring_phys = adapter->desc_pool.phys;
4432 offset = hw->rx_desc_info.alloc * hw->rx_desc_info.size;
4433 hw->tx_desc_info.ring_virt = (struct ksz_hw_desc *)
4435 hw->tx_desc_info.ring_phys = adapter->desc_pool.phys + offset;
4437 if (ksz_alloc_soft_desc(&hw->rx_desc_info, 0))
4439 if (ksz_alloc_soft_desc(&hw->tx_desc_info, 1))
4471 struct ksz_hw *hw = &adapter->hw;
4472 struct ksz_desc_info *info = &hw->rx_desc_info;
4474 for (i = 0; i < hw->rx_desc_info.alloc; i++) {
4510 struct ksz_hw *hw = &adapter->hw;
4513 hw->rx_desc_info.alloc = NUM_OF_RX_DESC;
4514 hw->tx_desc_info.alloc = NUM_OF_TX_DESC;
4517 hw->tx_int_cnt = 0;
4518 hw->tx_int_mask = NUM_OF_TX_DESC / 4;
4519 if (hw->tx_int_mask > 8)
4520 hw->tx_int_mask = 8;
4521 while (hw->tx_int_mask) {
4522 hw->tx_int_cnt++;
4523 hw->tx_int_mask >>= 1;
4525 if (hw->tx_int_cnt) {
4526 hw->tx_int_mask = (1 << (hw->tx_int_cnt - 1)) - 1;
4527 hw->tx_int_cnt = 0;
4531 hw->rx_desc_info.size =
4534 hw->tx_desc_info.size =
4537 if (hw->rx_desc_info.size != sizeof(struct ksz_hw_desc))
4539 ksz_check_desc_num(&hw->rx_desc_info);
4540 ksz_check_desc_num(&hw->tx_desc_info);
4558 struct ksz_hw *hw = &adapter->hw;
4561 hw->rx_desc_info.ring_virt = NULL;
4562 hw->tx_desc_info.ring_virt = NULL;
4563 hw->rx_desc_info.ring_phys = 0;
4564 hw->tx_desc_info.ring_phys = 0;
4578 kfree(hw->rx_desc_info.ring);
4579 hw->rx_desc_info.ring = NULL;
4580 kfree(hw->tx_desc_info.ring);
4581 hw->tx_desc_info.ring = NULL;
4615 ksz_free_buffers(adapter, &adapter->hw.tx_desc_info,
4619 ksz_free_buffers(adapter, &adapter->hw.rx_desc_info,
4626 static void get_mib_counters(struct ksz_hw *hw, int first, int cnt,
4636 port_mib = &hw->port_mib[port];
4637 for (mib = port_mib->mib_start; mib < hw->mib_cnt; mib++)
4655 struct ksz_hw *hw = &hw_priv->hw;
4656 struct ksz_desc_info *info = &hw->tx_desc_info;
4665 if (hw->dev_count > 1)
4666 hw->dst_ports = 1 << priv->port.first_port;
4696 ++hw->tx_int_cnt;
4743 hw_send_pkt(hw);
4760 struct ksz_hw *hw = &hw_priv->hw;
4761 struct ksz_desc_info *info = &hw->tx_desc_info;
4816 struct ksz_hw *hw = &hw_priv->hw;
4821 for (port = 0; port < hw->dev_count; port++) {
4822 struct net_device *dev = hw->port_info[port].pdev;
4853 struct ksz_hw *hw = &hw_priv->hw;
4858 if (hw->features & SMALL_PACKET_TX_BUG) {
4881 left = hw_alloc_pkt(hw, skb->len, num);
4927 struct ksz_hw *hw = &hw_priv->hw;
4930 if (hw->dev_count > 1) {
4941 hw_dis_intr(hw);
4942 hw_disable(hw);
4945 hw_reset_pkts(&hw->rx_desc_info);
4946 hw_reset_pkts(&hw->tx_desc_info);
4949 hw_reset(hw);
4951 hw_set_desc_base(hw,
4952 hw->tx_desc_info.ring_phys,
4953 hw->rx_desc_info.ring_phys);
4954 hw_set_addr(hw);
4955 if (hw->all_multi)
4956 hw_set_multicast(hw, hw->all_multi);
4957 else if (hw->multi_list_size)
4958 hw_set_grp_addr(hw);
4960 if (hw->dev_count > 1) {
4961 hw_set_add_addr(hw);
4965 port_set_stp_state(hw, port,
4968 port_dev = hw->port_info[port].pdev;
4970 port_set_stp_state(hw, port,
4975 hw_enable(hw);
4976 hw_ena_intr(hw);
5002 static inline int rx_proc(struct net_device *dev, struct ksz_hw* hw,
5040 if (hw->rx_cfg & (DMA_RX_CSUM_UDP | DMA_RX_CSUM_TCP))
5057 struct ksz_hw *hw = &hw_priv->hw;
5058 struct net_device *dev = hw->port_info[0].pdev;
5059 struct ksz_desc_info *info = &hw->rx_desc_info;
5074 if (rx_proc(dev, hw, desc, status))
5093 struct ksz_hw *hw = &hw_priv->hw;
5094 struct net_device *dev = hw->port_info[0].pdev;
5095 struct ksz_desc_info *info = &hw->rx_desc_info;
5108 if (hw->dev_count > 1) {
5112 dev = hw->port_info[p].pdev;
5119 if (rx_proc(dev, hw, desc, status))
5138 struct ksz_hw *hw = &hw_priv->hw;
5139 struct net_device *dev = hw->port_info[0].pdev;
5140 struct ksz_desc_info *info = &hw->rx_desc_info;
5153 if (hw->dev_count > 1) {
5157 dev = hw->port_info[p].pdev;
5172 if (rx_proc(dev, hw, desc, status))
5196 struct ksz_hw *hw = &hw_priv->hw;
5198 if (!hw->enabled)
5203 hw_resume_rx(hw);
5207 hw_turn_on_intr(hw, KS884X_INT_RX_MASK);
5210 hw_ack_intr(hw, KS884X_INT_RX);
5218 struct ksz_hw *hw = &hw_priv->hw;
5220 hw_ack_intr(hw, KS884X_INT_TX_MASK);
5226 hw_turn_on_intr(hw, KS884X_INT_TX);
5230 static inline void handle_rx_stop(struct ksz_hw *hw)
5233 if (0 == hw->rx_stop)
5234 hw->intr_mask &= ~KS884X_INT_RX_STOPPED;
5235 else if (hw->rx_stop > 1) {
5236 if (hw->enabled && (hw->rx_cfg & DMA_RX_ENABLE)) {
5237 hw_start_rx(hw);
5239 hw->intr_mask &= ~KS884X_INT_RX_STOPPED;
5240 hw->rx_stop = 0;
5244 hw->rx_stop++;
5262 struct ksz_hw *hw = &hw_priv->hw;
5264 hw_read_intr(hw, &int_enable);
5271 hw_ack_intr(hw, int_enable);
5272 int_enable &= hw->intr_mask;
5275 hw_dis_intr_bit(hw, KS884X_INT_TX_MASK);
5280 hw_dis_intr_bit(hw, KS884X_INT_RX);
5286 hw_resume_rx(hw);
5292 hw->features |= LINK_INT_WORKING;
5297 handle_rx_stop(hw);
5304 hw->intr_mask &= ~KS884X_INT_TX_STOPPED;
5306 data = readl(hw->io + KS_DMA_TX_CTRL);
5313 hw_ena_intr(hw);
5330 hw_dis_intr(&hw_priv->hw);
5335 static void bridge_change(struct ksz_hw *hw)
5339 struct ksz_switch *sw = hw->ksz_switch;
5343 port_set_stp_state(hw, SWITCH_PORT_NUM, STP_STATE_SIMPLE);
5344 sw_block_addr(hw);
5352 sw_cfg_port_base_vlan(hw, port, member);
5370 struct ksz_hw *hw = &hw_priv->hw;
5378 if (hw->dev_count > 1) {
5379 port_set_stp_state(hw, port->first_port, STP_STATE_DISABLED);
5382 if (hw->features & STP_SUPPORT) {
5384 if (hw->ksz_switch->member & pi) {
5385 hw->ksz_switch->member &= ~pi;
5386 bridge_change(hw);
5391 hw_del_addr(hw, dev->dev_addr);
5396 --hw->all_multi;
5398 --hw->promiscuous;
5405 hw_dis_intr(hw);
5406 hw_disable(hw);
5407 hw_clr_multicast(hw);
5417 hw_reset_pkts(&hw->rx_desc_info);
5418 hw_reset_pkts(&hw->tx_desc_info);
5421 if (hw->features & STP_SUPPORT)
5422 sw_clr_sta_mac_table(hw);
5428 static void hw_cfg_huge_frame(struct dev_info *hw_priv, struct ksz_hw *hw)
5430 if (hw->ksz_switch) {
5433 data = readw(hw->io + KS8842_SWITCH_CTRL_2_OFFSET);
5434 if (hw->features & RX_HUGE_FRAME)
5438 writew(data, hw->io + KS8842_SWITCH_CTRL_2_OFFSET);
5440 if (hw->features & RX_HUGE_FRAME) {
5441 hw->rx_cfg |= DMA_RX_ERROR;
5444 hw->rx_cfg &= ~DMA_RX_ERROR;
5445 if (hw->dev_count > 1)
5456 struct ksz_hw *hw = &hw_priv->hw;
5467 hw->promiscuous = 0;
5468 hw->all_multi = 0;
5469 hw->multi_list_size = 0;
5471 hw_reset(hw);
5473 hw_set_desc_base(hw,
5474 hw->tx_desc_info.ring_phys, hw->rx_desc_info.ring_phys);
5475 hw_set_addr(hw);
5476 hw_cfg_huge_frame(hw_priv, hw);
5506 struct ksz_hw *hw = &hw_priv->hw;
5524 for (i = 0; i < hw->mib_port_cnt; i++) {
5530 hw->port_mib[i].state = media_disconnected;
5531 port_init_cnt(hw, i);
5533 if (hw->ksz_switch)
5534 hw->port_mib[HOST_PORT].state = media_connected;
5536 hw_add_wol_bcast(hw);
5537 hw_cfg_wol_pme(hw, 0);
5538 hw_clr_wol_pme_status(&hw_priv->hw);
5548 hw->port_info[p].partner = 0xFF;
5549 hw->port_info[p].state = media_disconnected;
5553 if (hw->dev_count > 1) {
5554 port_set_stp_state(hw, port->first_port, STP_STATE_SIMPLE);
5556 hw_add_addr(hw, dev->dev_addr);
5566 hw_setup_intr(hw);
5567 hw_enable(hw);
5568 hw_ena_intr(hw);
5570 if (hw->mib_port_cnt)
5611 struct ksz_hw *hw = &priv->adapter->hw;
5628 mib = &hw->port_mib[p];
5667 struct ksz_hw *hw = &hw_priv->hw;
5672 hw_del_addr(hw, dev->dev_addr);
5674 hw->mac_override = 1;
5675 memcpy(hw->override_addr, mac->sa_data, ETH_ALEN);
5680 interrupt = hw_block_intr(hw);
5683 hw_add_addr(hw, dev->dev_addr);
5685 hw_set_addr(hw);
5686 hw_restore_intr(hw, interrupt);
5692 struct ksz_hw *hw, int promiscuous)
5695 u8 prev_state = hw->promiscuous;
5698 ++hw->promiscuous;
5700 --hw->promiscuous;
5704 if (hw->promiscuous <= 1 && prev_state <= 1)
5705 hw_set_promiscuous(hw, hw->promiscuous);
5711 if ((hw->features & STP_SUPPORT) && !promiscuous &&
5713 struct ksz_switch *sw = hw->ksz_switch;
5716 port_set_stp_state(hw, port, STP_STATE_DISABLED);
5720 bridge_change(hw);
5726 static void dev_set_multicast(struct dev_priv *priv, struct ksz_hw *hw,
5730 u8 all_multi = hw->all_multi;
5733 ++hw->all_multi;
5735 --hw->all_multi;
5739 if (hw->all_multi <= 1 && all_multi <= 1)
5740 hw_set_multicast(hw, hw->all_multi);
5755 struct ksz_hw *hw = &hw_priv->hw;
5759 dev_set_promiscuous(dev, priv, hw, (dev->flags & IFF_PROMISC));
5761 if (hw_priv->hw.dev_count > 1)
5763 dev_set_multicast(priv, hw, multicast);
5766 if (hw_priv->hw.dev_count > 1)
5774 if (MAX_MULTICAST_LIST != hw->multi_list_size) {
5775 hw->multi_list_size = MAX_MULTICAST_LIST;
5776 ++hw->all_multi;
5777 hw_set_multicast(hw, hw->all_multi);
5785 memcpy(hw->multi_list[i++], ha->addr, ETH_ALEN);
5787 hw->multi_list_size = (u8) i;
5788 hw_set_grp_addr(hw);
5790 if (MAX_MULTICAST_LIST == hw->multi_list_size) {
5791 --hw->all_multi;
5792 hw_set_multicast(hw, hw->all_multi);
5794 hw->multi_list_size = 0;
5795 hw_clr_multicast(hw);
5803 struct ksz_hw *hw = &hw_priv->hw;
5810 if (hw->dev_count > 1)
5821 hw->features |= RX_HUGE_FRAME;
5824 hw->features &= ~RX_HUGE_FRAME;
5848 struct ksz_hw *hw = &hw_priv->hw;
5871 hw_r_phy(hw, port->linked->port_id, data->reg_num,
5882 hw_w_phy(hw, port->linked->port_id, data->reg_num,
5913 struct ksz_hw *hw = port->hw;
5916 hw_r_phy(hw, port->linked->port_id, reg_num << 1, &val_out);
5933 struct ksz_hw *hw = port->hw;
5938 hw_w_phy(hw, pi, reg_num << 1, val);
6144 struct ksz_hw *hw = &hw_priv->hw;
6157 *buf = readl(hw->io + len);
6214 hw_enable_wol(&hw_priv->hw, hw_priv->wol_enable, net_addr);
6283 eeprom_data[i] = eeprom_read(&hw_priv->hw, i);
6315 eeprom_data[i] = eeprom_read(&hw_priv->hw, i);
6321 eeprom_write(&hw_priv->hw, i, eeprom_data[i]);
6339 struct ksz_hw *hw = &hw_priv->hw;
6341 pause->autoneg = (hw->overrides & PAUSE_FLOW_CTRL) ? 0 : 1;
6342 if (!hw->ksz_switch) {
6344 (hw->rx_cfg & DMA_RX_FLOW_ENABLE) ? 1 : 0;
6346 (hw->tx_cfg & DMA_TX_FLOW_ENABLE) ? 1 : 0;
6349 (sw_chk(hw, KS8842_SWITCH_CTRL_1_OFFSET,
6352 (sw_chk(hw, KS8842_SWITCH_CTRL_1_OFFSET,
6372 struct ksz_hw *hw = &hw_priv->hw;
6381 hw->overrides &= ~PAUSE_FLOW_CTRL;
6383 if (hw->ksz_switch) {
6384 sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET,
6386 sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET,
6391 hw->overrides |= PAUSE_FLOW_CTRL;
6392 if (hw->ksz_switch) {
6393 sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET,
6395 sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET,
6398 set_flow_ctrl(hw, pause->rx_pause, pause->tx_pause);
6417 struct ksz_hw *hw = &hw_priv->hw;
6420 ring->tx_pending = hw->tx_desc_info.alloc;
6422 ring->rx_pending = hw->rx_desc_info.alloc;
6480 struct ksz_hw *hw = &hw_priv->hw;
6484 ETH_GSTRING_LEN * hw->mib_cnt);
6500 struct ksz_hw *hw = &hw_priv->hw;
6504 return hw->mib_cnt;
6523 struct ksz_hw *hw = &hw_priv->hw;
6535 if (media_connected == hw->port_mib[p].state) {
6561 } else if (hw->port_mib[p].cnt_ptr) {
6569 get_mib_counters(hw, port->first_port, port->mib_port_cnt, counter);
6570 n = hw->mib_cnt;
6592 struct ksz_hw *hw = &hw_priv->hw;
6598 hw->rx_cfg |= DMA_RX_CSUM_TCP | DMA_RX_CSUM_IP;
6600 hw->rx_cfg &= ~(DMA_RX_CSUM_TCP | DMA_RX_CSUM_IP);
6602 if (hw->enabled)
6603 writel(hw->rx_cfg, hw->io + KS_DMA_RX_CTRL);
6651 struct ksz_hw *hw = &hw_priv->hw;
6656 for (i = 0; i < hw->mib_port_cnt; i++) {
6657 mib = &hw->port_mib[i];
6663 if (port_r_cnt(hw, i))
6677 next_jiffies += HZ * 1 * hw->mib_port_cnt;
6699 hw_clr_wol_pme_status(&hw_priv->hw);
6702 } else if (hw_chk_wol_pme_status(&hw_priv->hw)) {
6722 struct ksz_hw *hw = &hw_priv->hw;
6725 if (!(hw->features & LINK_INT_WORKING))
6879 hw_priv->hw.override_addr[j++] = (u8) num;
6880 hw_priv->hw.override_addr[5] +=
6881 hw_priv->hw.id;
6883 hw_priv->hw.ksz_switch->other_addr[j++] =
6885 hw_priv->hw.ksz_switch->other_addr[5] +=
6886 hw_priv->hw.id;
6894 hw_priv->hw.mac_override = 1;
6900 static void read_other_addr(struct ksz_hw *hw)
6904 struct ksz_switch *sw = hw->ksz_switch;
6907 data[i] = eeprom_read(hw, i + EEPROM_DATA_OTHER_MAC_ADDR);
6928 struct ksz_hw *hw;
6970 hw = &hw_priv->hw;
6972 hw->io = ioremap(reg_base, reg_len);
6973 if (!hw->io)
6976 cnt = hw_init(hw);
6987 dev_dbg(&hw_priv->pdev->dev, "Mem = %p; IRQ = %d\n", hw->io, pdev->irq);
6990 hw->dev_count = 1;
6993 hw->addr_list_size = 0;
6994 hw->mib_cnt = PORT_COUNTER_NUM;
6995 hw->mib_port_cnt = 1;
7000 hw->overrides |= FAST_AGING;
7002 hw->mib_cnt = TOTAL_PORT_COUNTER_NUM;
7006 hw->dev_count = SWITCH_PORT_NUM;
7007 hw->addr_list_size = SWITCH_PORT_NUM - 1;
7011 if (1 == hw->dev_count) {
7015 hw->mib_port_cnt = TOTAL_PORT_NUM;
7016 hw->ksz_switch = kzalloc(sizeof(struct ksz_switch), GFP_KERNEL);
7017 if (!hw->ksz_switch)
7020 sw = hw->ksz_switch;
7022 for (i = 0; i < hw->mib_port_cnt; i++)
7023 hw->port_mib[i].mib_start = 0;
7025 hw->parent = hw_priv;
7033 hw_priv->hw.id = net_device_present;
7055 hw_read_addr(hw);
7058 if (hw->dev_count > 1) {
7059 memcpy(sw->other_addr, hw->override_addr, ETH_ALEN);
7060 read_other_addr(hw);
7065 hw_setup(hw);
7066 if (hw->ksz_switch)
7067 sw_setup(hw);
7079 for (i = 0; i < hw->dev_count; i++) {
7095 port->hw = hw;
7096 port->linked = &hw->port_info[port->first_port];
7099 hw->port_info[pi].port_id = pi;
7100 hw->port_info[pi].pdev = dev;
7101 hw->port_info[pi].state = media_disconnected;
7104 dev->mem_start = (unsigned long) hw->io;
7108 memcpy(dev->dev_addr, hw_priv->hw.override_addr,
7112 if (!memcmp(sw->other_addr, hw->override_addr,
7129 for (i = 0; i < hw->dev_count; i++) {
7138 kfree(hw->ksz_switch);
7141 iounmap(hw->io);
7162 for (i = 0; i < hw_priv->hw.dev_count; i++) {
7166 if (hw_priv->hw.io)
7167 iounmap(hw_priv->hw.io);
7169 kfree(hw_priv->hw.ksz_switch);
7180 struct ksz_hw *hw = &hw_priv->hw;
7187 hw_cfg_wol_pme(hw, 0);
7188 for (i = 0; i < hw->dev_count; i++) {
7206 struct ksz_hw *hw = &hw_priv->hw;
7211 for (i = 0; i < hw->dev_count; i++) {
7222 hw_enable_wol(hw, hw_priv->wol_enable, net_addr);
7223 hw_cfg_wol_pme(hw, 1);