Lines Matching refs:fifo
1228 * __vxge_hw_device_fifo_config_check - Check fifo configuration.
1229 * Check the fifo configuration
1254 status = __vxge_hw_device_fifo_config_check(&vp_config->fifo);
1368 if (device_config->vp_config[i].fifo.enable ==
1370 nblocks += device_config->vp_config[i].fifo.fifo_blocks;
2954 device_config->vp_config[i].fifo.enable = VXGE_HW_FIFO_ENABLE;
2956 device_config->vp_config[i].fifo.fifo_blocks =
2959 device_config->vp_config[i].fifo.max_frags =
2962 device_config->vp_config[i].fifo.memblock_size =
2965 device_config->vp_config[i].fifo.alignment_size =
2968 device_config->vp_config[i].fifo.intr =
2971 device_config->vp_config[i].fifo.no_snoop_bits =
3349 * This function terminates the TxDs of fifo
3351 static enum vxge_hw_status __vxge_hw_fifo_abort(struct __vxge_hw_fifo *fifo)
3356 vxge_hw_channel_dtr_try_complete(&fifo->channel, &txdlh);
3361 vxge_hw_channel_dtr_complete(&fifo->channel);
3363 if (fifo->txdl_term) {
3364 fifo->txdl_term(txdlh,
3366 fifo->channel.userdata);
3369 vxge_hw_channel_dtr_free(&fifo->channel, txdlh);
3376 * __vxge_hw_fifo_reset - Resets the fifo
3377 * This function resets the fifo during vpath reset operation
3379 static enum vxge_hw_status __vxge_hw_fifo_reset(struct __vxge_hw_fifo *fifo)
3383 __vxge_hw_fifo_abort(fifo);
3384 status = __vxge_hw_channel_reset(&fifo->channel);
3396 struct __vxge_hw_fifo *fifo = vp->vpath->fifoh;
3398 __vxge_hw_fifo_abort(fifo);
3400 if (fifo->mempool)
3401 __vxge_hw_mempool_destroy(fifo->mempool);
3405 __vxge_hw_channel_free(&fifo->channel);
3426 struct __vxge_hw_fifo *fifo =
3436 txdl_priv = __vxge_hw_fifo_txdl_priv(fifo, txdp);
3440 fifo->channel.reserve_arr[fifo->channel.reserve_ptr - 1 - index] = txdp;
3461 struct __vxge_hw_fifo *fifo;
3472 config = &vpath->hldev->config.vp_config[vpath->vp_id].fifo;
3478 fifo = (struct __vxge_hw_fifo *)__vxge_hw_channel_allocate(vp,
3483 if (fifo == NULL) {
3488 vpath->fifoh = fifo;
3489 fifo->nofl_db = vpath->nofl_db;
3491 fifo->vp_id = vpath->vp_id;
3492 fifo->vp_reg = vpath->vp_reg;
3493 fifo->stats = &vpath->sw_stats->fifo_stats;
3495 fifo->config = config;
3498 fifo->interrupt_type = VXGE_HW_FIFO_TXD_INT_TYPE_UTILZ;
3499 fifo->tim_tti_cfg1_saved = vpath->tim_tti_cfg1_saved;
3500 fifo->tim_tti_cfg3_saved = vpath->tim_tti_cfg3_saved;
3502 if (fifo->config->intr)
3503 fifo->interrupt_type = VXGE_HW_FIFO_TXD_INT_TYPE_PER_LIST;
3505 fifo->no_snoop_bits = config->no_snoop_bits;
3527 fifo->priv_size =
3529 fifo->priv_size = ((fifo->priv_size + VXGE_CACHE_LINE_SIZE - 1) /
3532 fifo->per_txdl_space = attr->per_txdl_space;
3535 fifo->txdl_size = txdl_size;
3536 fifo->txdl_per_memblock = txdl_per_memblock;
3538 fifo->txdl_term = attr->txdl_term;
3539 fifo->callback = attr->callback;
3541 if (fifo->txdl_per_memblock == 0) {
3549 fifo->mempool =
3551 fifo->config->memblock_size,
3552 fifo->txdl_size,
3553 fifo->priv_size,
3554 (fifo->config->fifo_blocks * fifo->txdl_per_memblock),
3555 (fifo->config->fifo_blocks * fifo->txdl_per_memblock),
3557 fifo);
3559 if (fifo->mempool == NULL) {
3565 status = __vxge_hw_channel_initialize(&fifo->channel);
3571 vxge_assert(fifo->channel.reserve_ptr);
4175 if (vpath->vp_config->fifo.enable == VXGE_HW_FIFO_ENABLE) {
4180 ((vpath->vp_config->fifo.memblock_size /
4181 (vpath->vp_config->fifo.max_frags *
4183 vpath->vp_config->fifo.fifo_blocks)) {
4321 if (config->fifo.enable == VXGE_HW_FIFO_ENABLE) {
4841 if (vpath->vp_config->fifo.enable == VXGE_HW_FIFO_ENABLE) {