Cross Reference: /drivers/net/ethernet/neterion/vxge/vxge-main.c

Lines Matching defs:dtr
322 static inline void vxge_re_pre_post(void *dtr, struct vxge_ring *ring,
328 	vxge_hw_ring_rxd_1b_set(dtr, rx_priv->data_dma, rx_priv->data_size);
329 	vxge_hw_ring_rxd_pre_post(ring->handle, dtr);
353 vxge_rx_1b_compl(struct __vxge_hw_ring *ringh, void *dtr,
371 		prefetch((char *)dtr + L1_CACHE_BYTES);
372 		rx_priv = vxge_hw_ring_rxd_private_get(dtr);
382 		vxge_hw_ring_rxd_1b_get(ringh, dtr, &dma_sizes);
391 		vxge_hw_ring_rxd_1b_info_get(ringh, dtr, &ext_info);
398 			if (vxge_hw_ring_handle_tcode(ringh, dtr, t_code) !=
411 				vxge_re_pre_post(dtr, ring, rx_priv);
413 				vxge_post(&dtr_cnt, &first_dtr, dtr, ringh);
420 			if (vxge_rx_alloc(dtr, ring, data_size) != NULL) {
421 				if (!vxge_rx_map(dtr, ring)) {
427 					vxge_hw_ring_rxd_pre_post(ringh, dtr);
428 					vxge_post(&dtr_cnt, &first_dtr, dtr,
434 					vxge_re_pre_post(dtr, ring, rx_priv);
436 					vxge_post(&dtr_cnt, &first_dtr, dtr,
442 				vxge_re_pre_post(dtr, ring, rx_priv);
444 				vxge_post(&dtr_cnt, &first_dtr, dtr, ringh);
467 				vxge_re_pre_post(dtr, ring, rx_priv);
469 				vxge_post(&dtr_cnt, &first_dtr, dtr,
475 				vxge_re_pre_post(dtr, ring, rx_priv);
477 				vxge_post(&dtr_cnt, &first_dtr, dtr, ringh);
520 	} while (vxge_hw_ring_rxd_next_completed(ringh, &dtr,
541 vxge_xmit_compl(struct __vxge_hw_fifo *fifo_hw, void *dtr,
557 			vxge_hw_fifo_txdl_private_get(dtr);
564 				"%s: %s:%d fifo_hw = %p dtr = %p "
566 				__LINE__, fifo_hw, dtr, t_code);
576 				"%s: tx: dtr %p completed due to "
578 				dtr, t_code);
579 			vxge_hw_fifo_handle_tcode(fifo_hw, dtr, t_code);
593 		vxge_hw_fifo_txdl_free(fifo_hw, dtr);
613 				&dtr, &t_code) == VXGE_HW_OK);
805 	void *dtr = NULL;
878 	status = vxge_hw_fifo_txdl_reserve(fifo_hw, &dtr, &dtr_priv);
887 		"%s: %s:%d fifo_hw = %p dtr = %p dtr_priv = %p",
889 		fifo_hw, dtr, dtr_priv);
893 		vxge_hw_fifo_txdl_vlan_set(dtr, vlan_tag);
902 		vxge_hw_fifo_txdl_free(fifo_hw, dtr);
907 	txdl_priv = vxge_hw_fifo_txdl_private_get(dtr);
918 	vxge_hw_fifo_txdl_buffer_set(fifo_hw, dtr, j++, dma_pointer,
939 		vxge_hw_fifo_txdl_buffer_set(fifo_hw, dtr, j++, dma_pointer,
951 			vxge_hw_fifo_txdl_mss_set(dtr, mss);
961 		vxge_hw_fifo_txdl_cksum_set_bits(dtr,
966 	vxge_hw_fifo_txdl_post(fifo_hw, dtr);
987 	vxge_hw_fifo_txdl_free(fifo_hw, dtr);