Lines Matching refs:port
30 "Cavium Networks Octeon MII (management) port Network Driver"
63 int port;
92 int port = p->port;
97 mix_intena.u64 = cvmx_read_csr(CVMX_MIXX_INTENA(port));
99 cvmx_write_csr(CVMX_MIXX_INTENA(port), mix_intena.u64);
105 int port = p->port;
110 mix_intena.u64 = cvmx_read_csr(CVMX_MIXX_INTENA(port));
112 cvmx_write_csr(CVMX_MIXX_INTENA(port), mix_intena.u64);
149 int port = p->port;
180 cvmx_write_csr(CVMX_MIXX_IRING2(port), 1);
186 int port = p->port;
193 mix_orcnt.u64 = cvmx_read_csr(CVMX_MIXX_ORCNT(port));
197 mix_orcnt.u64 = cvmx_read_csr(CVMX_MIXX_ORCNT(port));
217 cvmx_write_csr(CVMX_MIXX_ORCNT(port), mix_orcnt.u64);
227 mix_orcnt.u64 = cvmx_read_csr(CVMX_MIXX_ORCNT(port));
244 int port = p->port;
249 drop = cvmx_read_csr(CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(port));
250 bad = cvmx_read_csr(CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(port));
264 int port = p->port;
271 s0.u64 = cvmx_read_csr(CVMX_AGL_GMX_TXX_STAT0(port));
272 s1.u64 = cvmx_read_csr(CVMX_AGL_GMX_TXX_STAT1(port));
311 int port = p->port;
384 cvmx_write_csr(CVMX_MIXX_IRCNT(port), mix_ircnt.u64);
390 int port = p->port;
395 mix_ircnt.u64 = cvmx_read_csr(CVMX_MIXX_IRCNT(port));
403 mix_ircnt.u64 = cvmx_read_csr(CVMX_MIXX_IRCNT(port));
437 cvmx_write_csr(CVMX_MIXX_CTL(p->port), mix_ctl.u64);
439 mix_ctl.u64 = cvmx_read_csr(CVMX_MIXX_CTL(p->port));
442 cvmx_write_csr(CVMX_MIXX_CTL(p->port), mix_ctl.u64);
443 cvmx_read_csr(CVMX_MIXX_CTL(p->port));
446 mix_bist.u64 = cvmx_read_csr(CVMX_MIXX_BIST(p->port));
477 int port = p->port;
523 agl_gmx_prtx.u64 = cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port));
526 cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), agl_gmx_prtx.u64);
533 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CTL(port), adr_ctl.u64);
535 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM0(port), cam_state.cam[0]);
536 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM1(port), cam_state.cam[1]);
537 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM2(port), cam_state.cam[2]);
538 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM3(port), cam_state.cam[3]);
539 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM4(port), cam_state.cam[4]);
540 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM5(port), cam_state.cam[5]);
541 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM_EN(port), cam_state.cam_mask);
545 cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), agl_gmx_prtx.u64);
567 int port = p->port;
583 cvmx_write_csr(CVMX_AGL_GMX_RXX_FRM_MAX(port), size_without_fcs);
584 cvmx_write_csr(CVMX_AGL_GMX_RXX_JABBER(port),
594 int port = p->port;
597 mixx_isr.u64 = cvmx_read_csr(CVMX_MIXX_ISR(port));
600 cvmx_write_csr(CVMX_MIXX_ISR(port), mixx_isr.u64);
601 cvmx_read_csr(CVMX_MIXX_ISR(port));
632 int port = p->port;
644 cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port));
646 cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port),
681 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, "mdio-octeon-0", p->port);
699 int port = p->port;
740 mix_ctl.u64 = cvmx_read_csr(CVMX_MIXX_CTL(port));
745 cvmx_write_csr(CVMX_MIXX_CTL(port), mix_ctl.u64);
747 mix_ctl.u64 = cvmx_read_csr(CVMX_MIXX_CTL(port));
758 cvmx_write_csr(CVMX_MIXX_ORING1(port), oring1.u64);
763 cvmx_write_csr(CVMX_MIXX_IRING1(port), iring1.u64);
766 prtx_cfg.u64 = cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port));
768 cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), prtx_cfg.u64);
776 * Enable the port HW. Packets are not allowed until
781 mix_ctl.s.en = 1; /* Enable the port */
785 cvmx_write_csr(CVMX_MIXX_CTL(port), mix_ctl.u64);
796 if (port) {
812 cvmx_write_csr(CVMX_AGL_GMX_RXX_STATS_CTL(port), 1);
813 cvmx_write_csr(CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(port), 0);
814 cvmx_write_csr(CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(port), 0);
816 cvmx_write_csr(CVMX_AGL_GMX_TXX_STATS_CTL(port), 1);
817 cvmx_write_csr(CVMX_AGL_GMX_TXX_STAT0(port), 0);
818 cvmx_write_csr(CVMX_AGL_GMX_TXX_STAT1(port), 0);
821 cvmx_write_csr(CVMX_MIXX_ISR(port), cvmx_read_csr(CVMX_MIXX_ISR(port)));
832 cvmx_write_csr(CVMX_MIXX_IRHWM(port), mix_irhwm.u64);
837 cvmx_write_csr(CVMX_MIXX_ORHWM(port), mix_orhwm.u64);
843 cvmx_write_csr(CVMX_MIXX_INTENA(port), mix_intena.u64);
870 * This port is configured to send PREAMBLE+SFD to begin every
874 cvmx_write_csr(CVMX_AGL_GMX_RXX_FRM_CTL(port), rxx_frm_ctl.u64);
881 /* Configure the port duplex and enables */
882 prtx_cfg.u64 = cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port));
888 cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), prtx_cfg.u64);
952 int port = p->port;
996 cvmx_write_csr(CVMX_MIXX_ORING2(port), 1);
1091 p->port = pdev->id;
1092 snprintf(netdev->name, IFNAMSIZ, "mgmt%d", p->port);
1114 netdev->dev_addr[5] += p->port;
1116 if (p->port >= octeon_bootinfo->mac_addr_count)