Lines Matching refs:ioaddr
193 static int atp_probe1(long ioaddr);
195 static unsigned short eeprom_op(long ioaddr, unsigned int cmd);
198 static void write_packet(long ioaddr, int length, unsigned char *packet, int pad, int mode);
199 static void trigger_send(long ioaddr, int length);
204 static void read_block(long ioaddr, int length, unsigned char *buffer, int data_mode);
232 long ioaddr = *port;
233 outb(0x57, ioaddr + PAR_DATA);
234 if (inb(ioaddr + PAR_DATA) != 0x57)
236 if (atp_probe1(ioaddr) == 0)
254 static int __init atp_probe1(long ioaddr)
261 outb(0xff, ioaddr + PAR_DATA);
264 saved_ctrl_reg = inb(ioaddr + PAR_CONTROL);
268 outb(0x04, ioaddr + PAR_CONTROL);
273 outb(mux_8012[i], ioaddr + PAR_DATA);
274 write_reg(ioaddr, MODSEL, 0x00);
277 printk(" %2.2x", read_nibble(ioaddr, i));
283 outb(mux_8012[i], ioaddr + PAR_DATA);
284 write_reg_high(ioaddr, CMR1, CMR1h_RESET);
286 status = read_nibble(ioaddr, CMR1);
291 printk(" %2.2x", read_nibble(ioaddr, i));
297 outb(saved_ctrl_reg, ioaddr + PAR_CONTROL);
300 status = read_nibble(ioaddr, CMR2_h);
302 outb(saved_ctrl_reg, ioaddr + PAR_CONTROL);
311 write_reg_byte(ioaddr, CMR2, 0x01); /* No accept mode, IRQ out. */
312 write_reg_high(ioaddr, CMR1, CMR1h_RxENABLE | CMR1h_TxENABLE); /* Enable Tx and Rx. */
317 else if (ioaddr == 0x378)
321 write_reg_high(ioaddr, CMR1, CMR1h_TxRxOFF); /* Disable Tx and Rx units. */
322 write_reg(ioaddr, CMR2, CMR2_NULL);
324 dev->base_addr = ioaddr;
339 write_reg_high(ioaddr, CMR1, CMR1h_RESET | CMR1h_MUX);
372 long ioaddr = dev->base_addr;
376 write_reg(ioaddr, CMR2, CMR2_EEPROM); /* Point to the EEPROM control registers. */
380 if (eeprom_op(ioaddr, EE_READ(0)) == 0xffff)
385 cpu_to_be16(eeprom_op(ioaddr, EE_READ(sa_offset + i)));
387 write_reg(ioaddr, CMR2, CMR2_NULL);
402 static unsigned short __init eeprom_op(long ioaddr, u32 cmd)
409 write_reg_high(ioaddr, PROM_CMD, outval | EE_CLK_LOW);
410 write_reg_high(ioaddr, PROM_CMD, outval | EE_CLK_HIGH);
412 if (read_nibble(ioaddr, PROM_DATA) & EE_DATA_READ)
415 write_reg_high(ioaddr, PROM_CMD, EE_CLK_LOW & ~EE_CS);
459 long ioaddr = dev->base_addr;
464 outb(mux_8012[i], ioaddr + PAR_DATA);
465 write_reg_high(ioaddr, CMR1, CMR1h_RESET);
468 write_reg_byte(ioaddr, PAR0 + i, dev->dev_addr[i]);
470 write_reg_high(ioaddr, CMR2, lp->addr_mode);
474 (read_nibble(ioaddr, CMR2_h) >> 3) & 0x0f);
477 write_reg(ioaddr, CMR2, CMR2_IRQOUT);
478 write_reg_high(ioaddr, CMR1, CMR1h_RxENABLE | CMR1h_TxENABLE);
481 outb(Ctrl_SelData + Ctrl_IRQEN, ioaddr + PAR_CONTROL);
484 write_reg(ioaddr, IMR, ISR_RxOK | ISR_TxErr | ISR_TxOK);
485 write_reg_high(ioaddr, IMR, ISRh_RxErr);
492 static void trigger_send(long ioaddr, int length)
494 write_reg_byte(ioaddr, TxCNT0, length & 0xff);
495 write_reg(ioaddr, TxCNT1, length >> 8);
496 write_reg(ioaddr, CMR1, CMR1_Xmit);
499 static void write_packet(long ioaddr, int length, unsigned char *packet, int pad_len, int data_mode)
507 outb(EOC+MAR, ioaddr + PAR_DATA);
510 outb(WrAddr+MAR, ioaddr + PAR_DATA);
512 write_byte_mode0(ioaddr, *packet++);
515 write_byte_mode0(ioaddr, 0);
521 outb(Ctrl_LNibWrite + Ctrl_IRQEN, ioaddr + PAR_CONTROL);
522 outb(WrAddr+MAR, ioaddr + PAR_DATA);
524 outb((outbyte & 0x0f)|0x40, ioaddr + PAR_DATA);
525 outb(outbyte & 0x0f, ioaddr + PAR_DATA);
527 outb(outbyte & 0x0f, ioaddr + PAR_DATA);
528 outb(Ctrl_HNibWrite + Ctrl_IRQEN, ioaddr + PAR_CONTROL);
530 write_byte_mode1(ioaddr, *packet++);
532 write_byte_mode1(ioaddr, 0);
535 outb(0xff, ioaddr + PAR_DATA);
536 outb(Ctrl_HNibWrite | Ctrl_SelData | Ctrl_IRQEN, ioaddr + PAR_CONTROL);
541 long ioaddr = dev->base_addr;
544 inb(ioaddr + PAR_CONTROL) & 0x10 ? "network cable problem"
558 long ioaddr = dev->base_addr;
570 write_reg(ioaddr, IMR, 0);
571 write_reg_high(ioaddr, IMR, 0);
574 write_packet(ioaddr, length, skb->data, length-skb->len, dev->if_port);
578 trigger_send(ioaddr, length);
585 write_reg(ioaddr, IMR, ISR_RxOK | ISR_TxErr | ISR_TxOK);
586 write_reg_high(ioaddr, IMR, ISRh_RxErr);
599 long ioaddr;
604 ioaddr = dev->base_addr;
610 outb(Ctrl_SelData, ioaddr + PAR_CONTROL);
613 write_reg(ioaddr, CMR2, CMR2_NULL);
614 write_reg(ioaddr, IMR, 0);
618 int status = read_nibble(ioaddr, ISR);
623 write_reg(ioaddr, ISR, ISR_RxOK); /* Clear the Rx interrupt. */
625 int read_status = read_nibble(ioaddr, CMR1);
633 write_reg_high(ioaddr, CMR2, CMR2h_OFF);
636 write_reg_high(ioaddr, ISR, ISRh_RxErr);
637 write_reg_high(ioaddr, CMR2, lp->addr_mode);
649 write_reg(ioaddr, ISR, ISR_TxErr + ISR_TxOK);
659 write_reg(ioaddr, CMR1, CMR1_ReXmit + CMR1_Xmit);
665 trigger_send(ioaddr, lp->saved_tx_size);
679 (read_nibble(ioaddr, CMR1) >> 3) & 15);
693 write_reg_byte(ioaddr, PAR0 + i, dev->dev_addr[i]);
700 write_reg(ioaddr, CMR2, CMR2_IRQOUT);
702 outb(Ctrl_SelData + Ctrl_IRQEN, ioaddr + PAR_CONTROL);
704 write_reg(ioaddr, IMR, ISR_RxOK | ISR_TxErr | ISR_TxOK);
705 write_reg_high(ioaddr, IMR, ISRh_RxErr); /* Hmmm, really needed? */
719 long ioaddr = dev->base_addr;
728 write_reg_byte(ioaddr, PAR0 + i, dev->dev_addr[i]);
732 if (read_cmd_byte(ioaddr, PAR0 + i) != atp_timed_dev->dev_addr[i])
735 write_reg_byte(ioaddr, PAR0 + i, atp_timed_dev->dev_addr[i]);
757 long ioaddr = dev->base_addr;
761 outb(EOC+MAR, ioaddr + PAR_DATA);
762 read_block(ioaddr, 8, (unsigned char*)&rx_head, dev->if_port);
775 write_reg_high(ioaddr, CMR1, CMR1h_TxENABLE);
776 write_reg_high(ioaddr, CMR1, CMR1h_RxENABLE | CMR1h_TxENABLE);
794 read_block(ioaddr, pkt_len, skb_put(skb,pkt_len), dev->if_port);
802 write_reg(ioaddr, CMR1, CMR1_NextPkt);
806 static void read_block(long ioaddr, int length, unsigned char *p, int data_mode)
809 outb(Ctrl_LNibRead, ioaddr + PAR_CONTROL);
811 ioaddr + PAR_DATA);
813 do { *p++ = read_byte_mode0(ioaddr); } while (--length > 0);
815 do { *p++ = read_byte_mode2(ioaddr); } while (--length > 0);
818 do { *p++ = read_byte_mode4(ioaddr); } while (--length > 0);
820 do { *p++ = read_byte_mode6(ioaddr); } while (--length > 0);
823 outb(EOC+HNib+MAR, ioaddr + PAR_DATA);
824 outb(Ctrl_SelData, ioaddr + PAR_CONTROL);
832 long ioaddr = dev->base_addr;
840 write_reg_high(ioaddr, CMR2, CMR2h_OFF);
843 outb(0x00, ioaddr + PAR_CONTROL);
847 write_reg_high(ioaddr, CMR1, CMR1h_RESET | CMR1h_MUX);
858 long ioaddr = dev->base_addr;
864 write_reg_high(ioaddr, CMR2, lp->addr_mode);
870 long ioaddr = dev->base_addr;
892 write_reg(ioaddr, CMR2, CMR2_IRQOUT | 0x04); /* Switch to page 1. */
894 write_reg_byte(ioaddr, i, mc_filter[i]);
904 write_reg_high(ioaddr, CMR2, lp->addr_mode);
905 write_reg(ioaddr, CMR2, CMR2_IRQOUT); /* Switch back to page 0 */