Lines Matching refs:tp
64 #define TX_SLOTS_AVAIL(tp) \
65 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
68 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
69 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
725 void (*phy_reset_enable)(struct rtl8169_private *tp);
727 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
729 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
776 static void rtl_lock_work(struct rtl8169_private *tp)
778 mutex_lock(&tp->wk.mutex);
781 static void rtl_unlock_work(struct rtl8169_private *tp)
783 mutex_unlock(&tp->wk.mutex);
799 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
801 void __iomem *ioaddr = tp->mmio_addr;
813 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
815 void __iomem *ioaddr = tp->mmio_addr;
827 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
829 void __iomem *ioaddr = tp->mmio_addr;
841 ocp_write(tp, 0x1, 0x30, 0x00000001);
848 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
850 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
853 static void rtl8168_driver_start(struct rtl8169_private *tp)
858 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
860 reg = rtl8168_get_ocp_reg(tp);
864 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
869 static void rtl8168_driver_stop(struct rtl8169_private *tp)
874 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
876 reg = rtl8168_get_ocp_reg(tp);
880 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
885 static int r8168dp_check_dash(struct rtl8169_private *tp)
887 u16 reg = rtl8168_get_ocp_reg(tp);
889 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
1015 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1017 tp->mdio_ops.write(tp->mmio_addr, location, val);
1020 static int rtl_readphy(struct rtl8169_private *tp, int location)
1022 return tp->mdio_ops.read(tp->mmio_addr, location);
1025 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1027 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1030 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1034 val = rtl_readphy(tp, reg_addr);
1035 rtl_writephy(tp, reg_addr, (val | p) & ~m);
1041 struct rtl8169_private *tp = netdev_priv(dev);
1043 rtl_writephy(tp, location, val);
1048 struct rtl8169_private *tp = netdev_priv(dev);
1050 return rtl_readphy(tp, location);
1195 static u16 rtl_get_events(struct rtl8169_private *tp)
1197 void __iomem *ioaddr = tp->mmio_addr;
1202 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1204 void __iomem *ioaddr = tp->mmio_addr;
1210 static void rtl_irq_disable(struct rtl8169_private *tp)
1212 void __iomem *ioaddr = tp->mmio_addr;
1218 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1220 void __iomem *ioaddr = tp->mmio_addr;
1229 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1231 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1234 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1236 void __iomem *ioaddr = tp->mmio_addr;
1238 rtl_irq_disable(tp);
1239 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1243 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1245 void __iomem *ioaddr = tp->mmio_addr;
1250 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1252 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1265 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1267 void __iomem *ioaddr = tp->mmio_addr;
1272 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1276 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1277 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1280 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1282 void __iomem *ioaddr = tp->mmio_addr;
1283 struct net_device *dev = tp->dev;
1288 if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
1310 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1311 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1327 struct rtl8169_private *tp,
1330 if (tp->link_ok(ioaddr)) {
1331 rtl_link_chg_patch(tp);
1334 pm_request_resume(&tp->pci_dev->dev);
1337 netif_info(tp, ifup, dev, "link up\n");
1340 netif_info(tp, ifdown, dev, "link down\n");
1342 pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1347 struct rtl8169_private *tp,
1350 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1355 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1357 void __iomem *ioaddr = tp->mmio_addr;
1384 struct rtl8169_private *tp = netdev_priv(dev);
1386 rtl_lock_work(tp);
1389 wol->wolopts = __rtl8169_get_wol(tp);
1391 rtl_unlock_work(tp);
1394 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1396 void __iomem *ioaddr = tp->mmio_addr;
1426 struct rtl8169_private *tp = netdev_priv(dev);
1428 rtl_lock_work(tp);
1431 tp->features |= RTL_FEATURE_WOL;
1433 tp->features &= ~RTL_FEATURE_WOL;
1434 __rtl8169_set_wol(tp, wol->wolopts);
1436 rtl_unlock_work(tp);
1438 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1443 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1445 return rtl_chip_infos[tp->mac_version].fw_name;
1451 struct rtl8169_private *tp = netdev_priv(dev);
1452 struct rtl_fw *rtl_fw = tp->rtl_fw;
1456 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1471 struct rtl8169_private *tp = netdev_priv(dev);
1472 void __iomem *ioaddr = tp->mmio_addr;
1483 netif_warn(tp, link, dev,
1494 struct rtl8169_private *tp = netdev_priv(dev);
1498 rtl_writephy(tp, 0x1f, 0x0000);
1503 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1518 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1522 if (tp->mii.supports_gmii) {
1529 netif_info(tp, link, dev,
1536 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1537 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1552 rtl_writephy(tp, MII_BMCR, bmcr);
1554 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1555 tp->mac_version == RTL_GIGA_MAC_VER_03) {
1557 rtl_writephy(tp, 0x17, 0x2138);
1558 rtl_writephy(tp, 0x0e, 0x0260);
1560 rtl_writephy(tp, 0x17, 0x2108);
1561 rtl_writephy(tp, 0x0e, 0x0000);
1573 struct rtl8169_private *tp = netdev_priv(dev);
1576 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1582 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1590 struct rtl8169_private *tp = netdev_priv(dev);
1593 del_timer_sync(&tp->timer);
1595 rtl_lock_work(tp);
1598 rtl_unlock_work(tp);
1606 struct rtl8169_private *tp = netdev_priv(dev);
1612 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1621 struct rtl8169_private *tp = netdev_priv(dev);
1623 void __iomem *ioaddr = tp->mmio_addr;
1630 tp->cp_cmd |= RxChkSum;
1632 tp->cp_cmd &= ~RxChkSum;
1635 tp->cp_cmd |= RxVlan;
1637 tp->cp_cmd &= ~RxVlan;
1639 RTL_W16(CPlusCmd, tp->cp_cmd);
1653 struct rtl8169_private *tp = netdev_priv(dev);
1655 rtl_lock_work(tp);
1657 rtl_unlock_work(tp);
1663 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1682 struct rtl8169_private *tp = netdev_priv(dev);
1683 void __iomem *ioaddr = tp->mmio_addr;
1703 struct rtl8169_private *tp = netdev_priv(dev);
1705 return mii_ethtool_gset(&tp->mii, cmd);
1710 struct rtl8169_private *tp = netdev_priv(dev);
1713 rtl_lock_work(tp);
1714 rc = tp->get_settings(dev, cmd);
1715 rtl_unlock_work(tp);
1723 struct rtl8169_private *tp = netdev_priv(dev);
1728 rtl_lock_work(tp);
1729 memcpy_fromio(p, tp->mmio_addr, regs->len);
1730 rtl_unlock_work(tp);
1735 struct rtl8169_private *tp = netdev_priv(dev);
1737 return tp->msg_enable;
1742 struct rtl8169_private *tp = netdev_priv(dev);
1744 tp->msg_enable = value;
1775 struct rtl8169_private *tp = netdev_priv(dev);
1776 void __iomem *ioaddr = tp->mmio_addr;
1777 struct device *d = &tp->pci_dev->dev;
1801 memcpy(&tp->counters, counters, sizeof(*counters));
1816 struct rtl8169_private *tp = netdev_priv(dev);
1822 data[0] = le64_to_cpu(tp->counters.tx_packets);
1823 data[1] = le64_to_cpu(tp->counters.rx_packets);
1824 data[2] = le64_to_cpu(tp->counters.tx_errors);
1825 data[3] = le32_to_cpu(tp->counters.rx_errors);
1826 data[4] = le16_to_cpu(tp->counters.rx_missed);
1827 data[5] = le16_to_cpu(tp->counters.align_errors);
1828 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1829 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1830 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1831 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1832 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1833 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1834 data[12] = le16_to_cpu(tp->counters.tx_underun);
1862 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1865 void __iomem *ioaddr = tp->mmio_addr;
1957 tp->mac_version = p->mac_version;
1959 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1960 netif_notice(tp, probe, dev,
1962 tp->mac_version = default_version;
1966 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1968 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1976 static void rtl_writephy_batch(struct rtl8169_private *tp,
1980 rtl_writephy(tp, regs->reg, regs->val);
2012 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2051 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2063 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2086 netif_err(tp, ifup, tp->dev,
2093 netif_err(tp, ifup, tp->dev,
2102 netif_err(tp, ifup, tp->dev,
2112 netif_err(tp, ifup, tp->dev,
2122 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2124 struct net_device *dev = tp->dev;
2127 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2128 netif_err(tp, ifup, dev, "invalid firwmare\n");
2132 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2138 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2156 predata = rtl_readphy(tp, regno);
2172 predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
2180 rtl_writephy(tp, regno, data);
2197 rtl_writephy(tp, regno, predata);
2217 static void rtl_release_firmware(struct rtl8169_private *tp)
2219 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2220 release_firmware(tp->rtl_fw->fw);
2221 kfree(tp->rtl_fw);
2223 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2226 static void rtl_apply_firmware(struct rtl8169_private *tp)
2228 struct rtl_fw *rtl_fw = tp->rtl_fw;
2232 rtl_phy_write_fw(tp, rtl_fw);
2235 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2237 if (rtl_readphy(tp, reg) != val)
2238 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2240 rtl_apply_firmware(tp);
2243 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2307 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2310 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2318 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2321 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2323 struct pci_dev *pdev = tp->pci_dev;
2329 rtl_writephy(tp, 0x1f, 0x0001);
2330 rtl_writephy(tp, 0x10, 0xf01b);
2331 rtl_writephy(tp, 0x1f, 0x0000);
2334 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2376 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2378 rtl8169scd_hw_phy_config_quirk(tp);
2381 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2431 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2434 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2441 rtl_writephy(tp, 0x1f, 0x0001);
2442 rtl_patchphy(tp, 0x16, 1 << 0);
2444 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2447 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2455 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2458 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2468 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2471 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2479 rtl_writephy(tp, 0x1f, 0x0000);
2480 rtl_patchphy(tp, 0x14, 1 << 5);
2481 rtl_patchphy(tp, 0x0d, 1 << 5);
2483 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2486 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2508 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2510 rtl_patchphy(tp, 0x14, 1 << 5);
2511 rtl_patchphy(tp, 0x0d, 1 << 5);
2512 rtl_writephy(tp, 0x1f, 0x0000);
2515 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2535 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2537 rtl_patchphy(tp, 0x16, 1 << 0);
2538 rtl_patchphy(tp, 0x14, 1 << 5);
2539 rtl_patchphy(tp, 0x0d, 1 << 5);
2540 rtl_writephy(tp, 0x1f, 0x0000);
2543 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2557 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2559 rtl_patchphy(tp, 0x16, 1 << 0);
2560 rtl_patchphy(tp, 0x14, 1 << 5);
2561 rtl_patchphy(tp, 0x0d, 1 << 5);
2562 rtl_writephy(tp, 0x1f, 0x0000);
2565 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2567 rtl8168c_3_hw_phy_config(tp);
2570 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2612 void __iomem *ioaddr = tp->mmio_addr;
2614 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2620 rtl_writephy(tp, 0x1f, 0x0002);
2621 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2622 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2635 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2637 val = rtl_readphy(tp, 0x0d);
2646 rtl_writephy(tp, 0x1f, 0x0002);
2650 rtl_writephy(tp, 0x0d, val | set[i]);
2661 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2665 rtl_writephy(tp, 0x1f, 0x0002);
2666 rtl_patchphy(tp, 0x0d, 0x0300);
2667 rtl_patchphy(tp, 0x0f, 0x0010);
2670 rtl_writephy(tp, 0x1f, 0x0002);
2671 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2672 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2674 rtl_writephy(tp, 0x1f, 0x0005);
2675 rtl_writephy(tp, 0x05, 0x001b);
2677 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2679 rtl_writephy(tp, 0x1f, 0x0000);
2682 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2724 void __iomem *ioaddr = tp->mmio_addr;
2726 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2740 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2742 val = rtl_readphy(tp, 0x0d);
2750 rtl_writephy(tp, 0x1f, 0x0002);
2754 rtl_writephy(tp, 0x0d, val | set[i]);
2765 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2769 rtl_writephy(tp, 0x1f, 0x0002);
2770 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2771 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2774 rtl_writephy(tp, 0x1f, 0x0002);
2775 rtl_patchphy(tp, 0x0f, 0x0017);
2777 rtl_writephy(tp, 0x1f, 0x0005);
2778 rtl_writephy(tp, 0x05, 0x001b);
2780 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2782 rtl_writephy(tp, 0x1f, 0x0000);
2785 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2843 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2846 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2858 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2859 rtl_patchphy(tp, 0x0d, 1 << 5);
2862 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
2892 rtl_apply_firmware(tp);
2894 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2897 rtl_writephy(tp, 0x1f, 0x0007);
2898 rtl_writephy(tp, 0x1e, 0x0023);
2899 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2900 rtl_writephy(tp, 0x1f, 0x0000);
2903 rtl_writephy(tp, 0x1f, 0x0002);
2904 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
2905 rtl_writephy(tp, 0x1f, 0x0000);
2908 rtl_writephy(tp, 0x1f, 0x0007);
2909 rtl_writephy(tp, 0x1e, 0x002d);
2910 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2911 rtl_writephy(tp, 0x1f, 0x0000);
2912 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2914 rtl_writephy(tp, 0x1f, 0x0005);
2915 rtl_writephy(tp, 0x05, 0x8b86);
2916 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2917 rtl_writephy(tp, 0x1f, 0x0000);
2919 rtl_writephy(tp, 0x1f, 0x0005);
2920 rtl_writephy(tp, 0x05, 0x8b85);
2921 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2922 rtl_writephy(tp, 0x1f, 0x0007);
2923 rtl_writephy(tp, 0x1e, 0x0020);
2924 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2925 rtl_writephy(tp, 0x1f, 0x0006);
2926 rtl_writephy(tp, 0x00, 0x5a00);
2927 rtl_writephy(tp, 0x1f, 0x0000);
2928 rtl_writephy(tp, 0x0d, 0x0007);
2929 rtl_writephy(tp, 0x0e, 0x003c);
2930 rtl_writephy(tp, 0x0d, 0x4007);
2931 rtl_writephy(tp, 0x0e, 0x0000);
2932 rtl_writephy(tp, 0x0d, 0x0000);
2935 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2964 rtl_apply_firmware(tp);
2966 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2969 rtl_writephy(tp, 0x1f, 0x0005);
2970 rtl_writephy(tp, 0x05, 0x8b80);
2971 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2972 rtl_writephy(tp, 0x1f, 0x0000);
2975 rtl_writephy(tp, 0x1f, 0x0004);
2976 rtl_writephy(tp, 0x1f, 0x0007);
2977 rtl_writephy(tp, 0x1e, 0x002d);
2978 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
2979 rtl_writephy(tp, 0x1f, 0x0002);
2980 rtl_writephy(tp, 0x1f, 0x0000);
2981 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2984 rtl_writephy(tp, 0x1f, 0x0005);
2985 rtl_writephy(tp, 0x05, 0x8b86);
2986 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2987 rtl_writephy(tp, 0x1f, 0x0000);
2990 rtl_writephy(tp, 0x1f, 0x0005);
2991 rtl_writephy(tp, 0x05, 0x8b85);
2992 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
2993 rtl_writephy(tp, 0x1f, 0x0000);
2996 rtl_w1w0_eri(tp->mmio_addr, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003,
2998 rtl_writephy(tp, 0x1f, 0x0005);
2999 rtl_writephy(tp, 0x05, 0x8b85);
3000 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3001 rtl_writephy(tp, 0x1f, 0x0004);
3002 rtl_writephy(tp, 0x1f, 0x0007);
3003 rtl_writephy(tp, 0x1e, 0x0020);
3004 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3005 rtl_writephy(tp, 0x1f, 0x0002);
3006 rtl_writephy(tp, 0x1f, 0x0000);
3007 rtl_writephy(tp, 0x0d, 0x0007);
3008 rtl_writephy(tp, 0x0e, 0x003c);
3009 rtl_writephy(tp, 0x0d, 0x4007);
3010 rtl_writephy(tp, 0x0e, 0x0000);
3011 rtl_writephy(tp, 0x0d, 0x0000);
3014 rtl_writephy(tp, 0x1f, 0x0003);
3015 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3016 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3017 rtl_writephy(tp, 0x1f, 0x0000);
3020 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3057 rtl_apply_firmware(tp);
3059 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3062 rtl_writephy(tp, 0x1f, 0x0005);
3063 rtl_writephy(tp, 0x05, 0x8b80);
3064 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3065 rtl_writephy(tp, 0x1f, 0x0000);
3068 rtl_writephy(tp, 0x1f, 0x0007);
3069 rtl_writephy(tp, 0x1e, 0x002d);
3070 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3071 rtl_writephy(tp, 0x1f, 0x0000);
3072 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3075 rtl_writephy(tp, 0x1f, 0x0005);
3076 rtl_writephy(tp, 0x05, 0x8b86);
3077 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3078 rtl_writephy(tp, 0x1f, 0x0000);
3081 rtl_writephy(tp, 0x1f, 0x0005);
3082 rtl_writephy(tp, 0x05, 0x8b85);
3083 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3084 rtl_writephy(tp, 0x1f, 0x0000);
3087 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3089 rtl_apply_firmware(tp);
3092 rtl_writephy(tp, 0x1f, 0x0005);
3093 rtl_writephy(tp, 0x05, 0x8b80);
3094 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3095 rtl_writephy(tp, 0x1f, 0x0000);
3098 rtl_writephy(tp, 0x1f, 0x0007);
3099 rtl_writephy(tp, 0x1e, 0x002d);
3100 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3101 rtl_writephy(tp, 0x1f, 0x0000);
3102 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3105 rtl_writephy(tp, 0x1f, 0x0005);
3106 rtl_writephy(tp, 0x05, 0x8b86);
3107 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3108 rtl_writephy(tp, 0x1f, 0x0000);
3111 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3120 rtl_writephy(tp, 0x1f, 0x0000);
3121 rtl_patchphy(tp, 0x11, 1 << 12);
3122 rtl_patchphy(tp, 0x19, 1 << 13);
3123 rtl_patchphy(tp, 0x10, 1 << 15);
3125 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3128 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3145 rtl_writephy(tp, 0x1f, 0x0000);
3146 rtl_writephy(tp, 0x18, 0x0310);
3149 rtl_apply_firmware(tp);
3151 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3156 struct rtl8169_private *tp = netdev_priv(dev);
3158 rtl8169_print_mac_version(tp);
3160 switch (tp->mac_version) {
3165 rtl8169s_hw_phy_config(tp);
3168 rtl8169sb_hw_phy_config(tp);
3171 rtl8169scd_hw_phy_config(tp);
3174 rtl8169sce_hw_phy_config(tp);
3179 rtl8102e_hw_phy_config(tp);
3182 rtl8168bb_hw_phy_config(tp);
3185 rtl8168bef_hw_phy_config(tp);
3188 rtl8168bef_hw_phy_config(tp);
3191 rtl8168cp_1_hw_phy_config(tp);
3194 rtl8168c_1_hw_phy_config(tp);
3197 rtl8168c_2_hw_phy_config(tp);
3200 rtl8168c_3_hw_phy_config(tp);
3203 rtl8168c_4_hw_phy_config(tp);
3207 rtl8168cp_2_hw_phy_config(tp);
3210 rtl8168d_1_hw_phy_config(tp);
3213 rtl8168d_2_hw_phy_config(tp);
3216 rtl8168d_3_hw_phy_config(tp);
3219 rtl8168d_4_hw_phy_config(tp);
3223 rtl8105e_hw_phy_config(tp);
3230 rtl8168e_1_hw_phy_config(tp);
3233 rtl8168e_2_hw_phy_config(tp);
3236 rtl8168f_1_hw_phy_config(tp);
3239 rtl8168f_2_hw_phy_config(tp);
3247 static void rtl_phy_work(struct rtl8169_private *tp)
3249 struct timer_list *timer = &tp->timer;
3250 void __iomem *ioaddr = tp->mmio_addr;
3253 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
3255 if (tp->phy_reset_pending(tp)) {
3264 if (tp->link_ok(ioaddr))
3267 netif_warn(tp, link, tp->dev, "PHY reset until link up\n");
3269 tp->phy_reset_enable(tp);
3275 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3277 if (!test_and_set_bit(flag, tp->wk.flags))
3278 schedule_work(&tp->wk.work);
3284 struct rtl8169_private *tp = netdev_priv(dev);
3286 rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
3300 struct rtl8169_private *tp)
3304 tp->phy_reset_enable(tp);
3306 if (!tp->phy_reset_pending(tp))
3310 netif_err(tp, link, dev, "PHY reset failed\n");
3313 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3315 void __iomem *ioaddr = tp->mmio_addr;
3317 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3321 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3323 void __iomem *ioaddr = tp->mmio_addr;
3327 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3332 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3334 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3335 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3337 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
3341 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
3344 rtl8169_phy_reset(dev, tp);
3349 (tp->mii.supports_gmii ?
3353 if (rtl_tbi_enabled(tp))
3354 netif_info(tp, link, dev, "TBI auto-negotiating\n");
3357 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3359 void __iomem *ioaddr = tp->mmio_addr;
3366 rtl_lock_work(tp);
3376 if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
3390 rtl_unlock_work(tp);
3395 struct rtl8169_private *tp = netdev_priv(dev);
3403 rtl_rar_set(tp, dev->dev_addr);
3410 struct rtl8169_private *tp = netdev_priv(dev);
3413 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3416 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3425 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
3429 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
3435 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3440 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3442 if (tp->features & RTL_FEATURE_MSI) {
3444 tp->features &= ~RTL_FEATURE_MSI;
3448 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3450 struct mdio_ops *ops = &tp->mdio_ops;
3452 switch (tp->mac_version) {
3469 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3471 void __iomem *ioaddr = tp->mmio_addr;
3473 switch (tp->mac_version) {
3487 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
3489 if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
3492 rtl_writephy(tp, 0x1f, 0x0000);
3493 rtl_writephy(tp, MII_BMCR, 0x0000);
3495 rtl_wol_suspend_quirk(tp);
3500 static void r810x_phy_power_down(struct rtl8169_private *tp)
3502 rtl_writephy(tp, 0x1f, 0x0000);
3503 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3506 static void r810x_phy_power_up(struct rtl8169_private *tp)
3508 rtl_writephy(tp, 0x1f, 0x0000);
3509 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3512 static void r810x_pll_power_down(struct rtl8169_private *tp)
3514 if (rtl_wol_pll_power_down(tp))
3517 r810x_phy_power_down(tp);
3520 static void r810x_pll_power_up(struct rtl8169_private *tp)
3522 r810x_phy_power_up(tp);
3525 static void r8168_phy_power_up(struct rtl8169_private *tp)
3527 rtl_writephy(tp, 0x1f, 0x0000);
3528 switch (tp->mac_version) {
3544 rtl_writephy(tp, 0x0e, 0x0000);
3549 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3552 static void r8168_phy_power_down(struct rtl8169_private *tp)
3554 rtl_writephy(tp, 0x1f, 0x0000);
3555 switch (tp->mac_version) {
3558 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3576 rtl_writephy(tp, 0x0e, 0x0200);
3578 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3583 static void r8168_pll_power_down(struct rtl8169_private *tp)
3585 void __iomem *ioaddr = tp->mmio_addr;
3587 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3588 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3589 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3590 r8168dp_check_dash(tp)) {
3594 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3595 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
3600 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3601 tp->mac_version == RTL_GIGA_MAC_VER_33)
3604 if (rtl_wol_pll_power_down(tp))
3607 r8168_phy_power_down(tp);
3609 switch (tp->mac_version) {
3622 static void r8168_pll_power_up(struct rtl8169_private *tp)
3624 void __iomem *ioaddr = tp->mmio_addr;
3626 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3627 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3628 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3629 r8168dp_check_dash(tp)) {
3633 switch (tp->mac_version) {
3645 r8168_phy_power_up(tp);
3648 static void rtl_generic_op(struct rtl8169_private *tp,
3652 op(tp);
3655 static void rtl_pll_power_down(struct rtl8169_private *tp)
3657 rtl_generic_op(tp, tp->pll_power_ops.down);
3660 static void rtl_pll_power_up(struct rtl8169_private *tp)
3662 rtl_generic_op(tp, tp->pll_power_ops.up);
3665 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3667 struct pll_power_ops *ops = &tp->pll_power_ops;
3669 switch (tp->mac_version) {
3712 static void rtl_init_rxcfg(struct rtl8169_private *tp)
3714 void __iomem *ioaddr = tp->mmio_addr;
3716 switch (tp->mac_version) {
3748 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3750 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3753 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
3755 void __iomem *ioaddr = tp->mmio_addr;
3758 rtl_generic_op(tp, tp->jumbo_ops.enable);
3762 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
3764 void __iomem *ioaddr = tp->mmio_addr;
3767 rtl_generic_op(tp, tp->jumbo_ops.disable);
3771 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
3773 void __iomem *ioaddr = tp->mmio_addr;
3777 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
3780 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
3782 void __iomem *ioaddr = tp->mmio_addr;
3786 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
3789 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
3791 void __iomem *ioaddr = tp->mmio_addr;
3796 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
3798 void __iomem *ioaddr = tp->mmio_addr;
3803 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
3805 void __iomem *ioaddr = tp->mmio_addr;
3810 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
3813 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
3815 void __iomem *ioaddr = tp->mmio_addr;
3820 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
3823 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
3825 rtl_tx_performance_tweak(tp->pci_dev,
3829 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
3831 rtl_tx_performance_tweak(tp->pci_dev,
3835 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
3837 void __iomem *ioaddr = tp->mmio_addr;
3839 r8168b_0_hw_jumbo_enable(tp);
3844 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
3846 void __iomem *ioaddr = tp->mmio_addr;
3848 r8168b_0_hw_jumbo_disable(tp);
3853 static void __devinit rtl_init_jumbo_ops(struct rtl8169_private *tp)
3855 struct jumbo_ops *ops = &tp->jumbo_ops;
3857 switch (tp->mac_version) {
3903 static void rtl_hw_reset(struct rtl8169_private *tp)
3905 void __iomem *ioaddr = tp->mmio_addr;
3919 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
3925 name = rtl_lookup_firmware_name(tp);
3933 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
3937 rc = rtl_check_firmware(tp, rtl_fw);
3941 tp->rtl_fw = rtl_fw;
3950 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
3953 tp->rtl_fw = NULL;
3957 static void rtl_request_firmware(struct rtl8169_private *tp)
3959 if (IS_ERR(tp->rtl_fw))
3960 rtl_request_uncached_firmware(tp);
3963 static void rtl_rx_close(struct rtl8169_private *tp)
3965 void __iomem *ioaddr = tp->mmio_addr;
3970 static void rtl8169_hw_reset(struct rtl8169_private *tp)
3972 void __iomem *ioaddr = tp->mmio_addr;
3975 rtl8169_irq_mask_and_ack(tp);
3977 rtl_rx_close(tp);
3979 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3980 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3981 tp->mac_version == RTL_GIGA_MAC_VER_31) {
3984 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
3985 tp->mac_version == RTL_GIGA_MAC_VER_35 ||
3986 tp->mac_version == RTL_GIGA_MAC_VER_36) {
3995 rtl_hw_reset(tp);
3998 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
4000 void __iomem *ioaddr = tp->mmio_addr;
4009 struct rtl8169_private *tp = netdev_priv(dev);
4011 tp->hw_start(dev);
4013 rtl_irq_enable_all(tp);
4016 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4024 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4025 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4026 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4027 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4072 struct rtl8169_private *tp = netdev_priv(dev);
4073 void __iomem *ioaddr = tp->mmio_addr;
4080 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4107 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4122 struct rtl8169_private *tp = netdev_priv(dev);
4123 void __iomem *ioaddr = tp->mmio_addr;
4124 struct pci_dev *pdev = tp->pci_dev;
4126 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4132 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4133 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4134 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4135 tp->mac_version == RTL_GIGA_MAC_VER_04)
4138 rtl_init_rxcfg(tp);
4144 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4145 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4146 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4147 tp->mac_version == RTL_GIGA_MAC_VER_04)
4148 rtl_set_rx_tx_config_registers(tp);
4150 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
4152 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4153 tp->mac_version == RTL_GIGA_MAC_VER_03) {
4156 tp->cp_cmd |= (1 << 14);
4159 RTL_W16(CPlusCmd, tp->cp_cmd);
4161 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4169 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4171 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4172 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4173 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4174 tp->mac_version != RTL_GIGA_MAC_VER_04) {
4176 rtl_set_rx_tx_config_registers(tp);
4551 struct rtl8169_private *tp = netdev_priv(dev);
4552 void __iomem *ioaddr = tp->mmio_addr;
4553 struct pci_dev *pdev = tp->pci_dev;
4561 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
4563 RTL_W16(CPlusCmd, tp->cp_cmd);
4568 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
4569 tp->event_slow |= RxFIFOOver | PCSTimeout;
4570 tp->event_slow &= ~RxOverflow;
4573 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4582 switch (tp->mac_version) {
4649 dev->name, tp->mac_version);
4752 struct rtl8169_private *tp = netdev_priv(dev);
4753 void __iomem *ioaddr = tp->mmio_addr;
4754 struct pci_dev *pdev = tp->pci_dev;
4756 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
4757 tp->event_slow &= ~RxFIFOOver;
4759 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
4760 tp->mac_version == RTL_GIGA_MAC_VER_16) {
4771 switch (tp->mac_version) {
4798 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
4799 RTL_W16(CPlusCmd, tp->cp_cmd);
4803 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4806 rtl_set_rx_tx_config_registers(tp);
4817 struct rtl8169_private *tp = netdev_priv(dev);
4820 new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
4824 rtl_hw_jumbo_enable(tp);
4826 rtl_hw_jumbo_disable(tp);
4840 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4843 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
4871 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4876 struct device *d = &tp->pci_dev->dev;
4877 struct net_device *dev = tp->dev;
4895 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
4907 static void rtl8169_rx_clear(struct rtl8169_private *tp)
4912 if (tp->Rx_databuff[i]) {
4913 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
4914 tp->RxDescArray + i);
4924 static int rtl8169_rx_fill(struct rtl8169_private *tp)
4931 if (tp->Rx_databuff[i])
4934 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
4936 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
4939 tp->Rx_databuff[i] = data;
4942 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4946 rtl8169_rx_clear(tp);
4952 struct rtl8169_private *tp = netdev_priv(dev);
4954 rtl8169_init_ring_indexes(tp);
4956 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4957 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
4959 return rtl8169_rx_fill(tp);
4975 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4982 struct ring_info *tx_skb = tp->tx_skb + entry;
4988 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4989 tp->TxDescArray + entry);
4991 tp->dev->stats.tx_dropped++;
4999 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5001 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5002 tp->cur_tx = tp->dirty_tx = 0;
5003 netdev_reset_queue(tp->dev);
5006 static void rtl_reset_work(struct rtl8169_private *tp)
5008 struct net_device *dev = tp->dev;
5011 napi_disable(&tp->napi);
5015 rtl8169_hw_reset(tp);
5018 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5020 rtl8169_tx_clear(tp);
5021 rtl8169_init_ring_indexes(tp);
5023 napi_enable(&tp->napi);
5026 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
5031 struct rtl8169_private *tp = netdev_priv(dev);
5033 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5036 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5042 struct device *d = &tp->pci_dev->dev;
5044 entry = tp->cur_tx;
5053 txd = tp->TxDescArray + entry;
5059 netif_err(tp, drv, tp->dev,
5072 tp->tx_skb[entry].len = len;
5076 tp->tx_skb[entry].skb = skb;
5083 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5087 static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
5090 const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
5112 struct rtl8169_private *tp = netdev_priv(dev);
5113 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5114 struct TxDesc *txd = tp->TxDescArray + entry;
5115 void __iomem *ioaddr = tp->mmio_addr;
5116 struct device *d = &tp->pci_dev->dev;
5122 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
5123 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5134 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5138 tp->tx_skb[entry].len = len;
5141 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
5144 rtl8169_tso_csum(tp, skb, opts);
5146 frags = rtl8169_xmit_frags(tp, skb, opts);
5153 tp->tx_skb[entry].skb = skb;
5168 tp->cur_tx += frags + 1;
5176 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
5190 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
5197 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
5211 struct rtl8169_private *tp = netdev_priv(dev);
5212 struct pci_dev *pdev = tp->pci_dev;
5218 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5242 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
5243 void __iomem *ioaddr = tp->mmio_addr;
5245 netif_info(tp, intr, dev, "disabling PCI DAC\n");
5246 tp->cp_cmd &= ~PCIDAC;
5247 RTL_W16(CPlusCmd, tp->cp_cmd);
5251 rtl8169_hw_reset(tp);
5253 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5261 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
5263 struct rtl8169_stats *tx_stats = &tp->tx_stats;
5267 dirty_tx = tp->dirty_tx;
5269 tx_left = tp->cur_tx - dirty_tx;
5273 struct ring_info *tx_skb = tp->tx_skb + entry;
5277 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5281 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5282 tp->TxDescArray + entry);
5302 if (tp->dirty_tx != dirty_tx) {
5303 tp->dirty_tx = dirty_tx;
5313 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
5322 if (tp->cur_tx != dirty_tx) {
5323 void __iomem *ioaddr = tp->mmio_addr;
5347 struct rtl8169_private *tp,
5352 struct device *d = &tp->pci_dev->dev;
5357 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
5365 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
5370 cur_rx = tp->cur_rx;
5371 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
5376 struct RxDesc *desc = tp->RxDescArray + entry;
5380 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
5385 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5393 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5426 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5427 tp, pkt_size, addr);
5440 napi_gro_receive(&tp->napi, skb);
5442 u64_stats_update_begin(&tp->rx_stats.syncp);
5443 tp->rx_stats.packets++;
5444 tp->rx_stats.bytes += pkt_size;
5445 u64_stats_update_end(&tp->rx_stats.syncp);
5450 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
5456 count = cur_rx - tp->cur_rx;
5457 tp->cur_rx = cur_rx;
5459 tp->dirty_rx += count;
5467 struct rtl8169_private *tp = netdev_priv(dev);
5471 status = rtl_get_events(tp);
5473 status &= RTL_EVENT_NAPI | tp->event_slow;
5477 rtl_irq_disable(tp);
5478 napi_schedule(&tp->napi);
5487 static void rtl_slow_event_work(struct rtl8169_private *tp)
5489 struct net_device *dev = tp->dev;
5492 status = rtl_get_events(tp) & tp->event_slow;
5493 rtl_ack_events(tp, status);
5496 switch (tp->mac_version) {
5501 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
5511 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
5513 napi_disable(&tp->napi);
5514 rtl_irq_disable(tp);
5516 napi_enable(&tp->napi);
5517 napi_schedule(&tp->napi);
5531 struct rtl8169_private *tp =
5533 struct net_device *dev = tp->dev;
5536 rtl_lock_work(tp);
5539 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
5545 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
5547 rtl_work[i].action(tp);
5551 rtl_unlock_work(tp);
5556 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5557 struct net_device *dev = tp->dev;
5558 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
5562 status = rtl_get_events(tp);
5563 rtl_ack_events(tp, status & ~tp->event_slow);
5566 work_done = rtl_rx(dev, tp, (u32) budget);
5569 rtl_tx(dev, tp);
5571 if (status & tp->event_slow) {
5572 enable_mask &= ~tp->event_slow;
5574 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
5580 rtl_irq_enable(tp, enable_mask);
5589 struct rtl8169_private *tp = netdev_priv(dev);
5591 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5600 struct rtl8169_private *tp = netdev_priv(dev);
5601 void __iomem *ioaddr = tp->mmio_addr;
5603 del_timer_sync(&tp->timer);
5605 napi_disable(&tp->napi);
5608 rtl8169_hw_reset(tp);
5619 rtl8169_tx_clear(tp);
5621 rtl8169_rx_clear(tp);
5623 rtl_pll_power_down(tp);
5628 struct rtl8169_private *tp = netdev_priv(dev);
5629 struct pci_dev *pdev = tp->pci_dev;
5636 rtl_lock_work(tp);
5637 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
5640 rtl_unlock_work(tp);
5644 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5645 tp->RxPhyAddr);
5646 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5647 tp->TxPhyAddr);
5648 tp->TxDescArray = NULL;
5649 tp->RxDescArray = NULL;
5659 struct rtl8169_private *tp = netdev_priv(dev);
5661 rtl8169_interrupt(tp->pci_dev->irq, dev);
5667 struct rtl8169_private *tp = netdev_priv(dev);
5668 void __iomem *ioaddr = tp->mmio_addr;
5669 struct pci_dev *pdev = tp->pci_dev;
5678 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
5679 &tp->TxPhyAddr, GFP_KERNEL);
5680 if (!tp->TxDescArray)
5683 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
5684 &tp->RxPhyAddr, GFP_KERNEL);
5685 if (!tp->RxDescArray)
5692 INIT_WORK(&tp->wk.work, rtl_task);
5696 rtl_request_firmware(tp);
5699 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
5704 rtl_lock_work(tp);
5706 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
5708 napi_enable(&tp->napi);
5710 rtl8169_init_phy(dev, tp);
5714 rtl_pll_power_up(tp);
5720 rtl_unlock_work(tp);
5722 tp->saved_wolopts = 0;
5725 rtl8169_check_link_status(dev, tp, ioaddr);
5730 rtl_release_firmware(tp);
5731 rtl8169_rx_clear(tp);
5733 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5734 tp->RxPhyAddr);
5735 tp->RxDescArray = NULL;
5737 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5738 tp->TxPhyAddr);
5739 tp->TxDescArray = NULL;
5748 struct rtl8169_private *tp = netdev_priv(dev);
5749 void __iomem *ioaddr = tp->mmio_addr;
5756 start = u64_stats_fetch_begin_bh(&tp->rx_stats.syncp);
5757 stats->rx_packets = tp->rx_stats.packets;
5758 stats->rx_bytes = tp->rx_stats.bytes;
5759 } while (u64_stats_fetch_retry_bh(&tp->rx_stats.syncp, start));
5763 start = u64_stats_fetch_begin_bh(&tp->tx_stats.syncp);
5764 stats->tx_packets = tp->tx_stats.packets;
5765 stats->tx_bytes = tp->tx_stats.bytes;
5766 } while (u64_stats_fetch_retry_bh(&tp->tx_stats.syncp, start));
5781 struct rtl8169_private *tp = netdev_priv(dev);
5789 rtl_lock_work(tp);
5790 napi_disable(&tp->napi);
5791 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
5792 rtl_unlock_work(tp);
5794 rtl_pll_power_down(tp);
5811 struct rtl8169_private *tp = netdev_priv(dev);
5815 rtl_pll_power_up(tp);
5817 rtl_lock_work(tp);
5818 napi_enable(&tp->napi);
5819 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
5820 rtl_unlock_work(tp);
5822 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5829 struct rtl8169_private *tp = netdev_priv(dev);
5831 rtl8169_init_phy(dev, tp);
5843 struct rtl8169_private *tp = netdev_priv(dev);
5845 if (!tp->TxDescArray)
5848 rtl_lock_work(tp);
5849 tp->saved_wolopts = __rtl8169_get_wol(tp);
5850 __rtl8169_set_wol(tp, WAKE_ANY);
5851 rtl_unlock_work(tp);
5862 struct rtl8169_private *tp = netdev_priv(dev);
5864 if (!tp->TxDescArray)
5867 rtl_lock_work(tp);
5868 __rtl8169_set_wol(tp, tp->saved_wolopts);
5869 tp->saved_wolopts = 0;
5870 rtl_unlock_work(tp);
5872 rtl8169_init_phy(dev, tp);
5883 struct rtl8169_private *tp = netdev_priv(dev);
5885 return tp->TxDescArray ? -EBUSY : 0;
5908 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
5910 void __iomem *ioaddr = tp->mmio_addr;
5913 switch (tp->mac_version) {
5917 pci_clear_master(tp->pci_dev);
5931 struct rtl8169_private *tp = netdev_priv(dev);
5939 rtl_rar_set(tp, dev->perm_addr);
5941 rtl8169_hw_reset(tp);
5944 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
5945 rtl_wol_suspend_quirk(tp);
5946 rtl_wol_shutdown_quirk(tp);
5959 struct rtl8169_private *tp = netdev_priv(dev);
5961 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
5962 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
5963 tp->mac_version == RTL_GIGA_MAC_VER_31) {
5964 rtl8168_driver_stop(tp);
5967 cancel_work_sync(&tp->wk.work);
5969 netif_napi_del(&tp->napi);
5973 rtl_release_firmware(tp);
5979 rtl_rar_set(tp, dev->perm_addr);
5981 rtl_disable_msi(pdev, tp);
5982 rtl8169_release_board(pdev, dev, tp->mmio_addr);
6041 static unsigned rtl_try_msi(struct rtl8169_private *tp,
6044 void __iomem *ioaddr = tp->mmio_addr;
6050 if (pci_enable_msi(tp->pci_dev)) {
6051 netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
6057 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
6067 struct rtl8169_private *tp;
6079 dev = alloc_etherdev(sizeof (*tp));
6087 tp = netdev_priv(dev);
6088 tp->dev = dev;
6089 tp->pci_dev = pdev;
6090 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
6092 mii = &tp->mii;
6108 netif_err(tp, probe, dev, "enable failure\n");
6113 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
6117 netif_err(tp, probe, dev,
6126 netif_err(tp, probe, dev,
6134 netif_err(tp, probe, dev, "could not request regions\n");
6138 tp->cp_cmd = RxChkSum;
6142 tp->cp_cmd |= PCIDAC;
6147 netif_err(tp, probe, dev, "DMA configuration failed\n");
6155 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
6159 tp->mmio_addr = ioaddr;
6162 netif_info(tp, probe, dev, "not PCI Express\n");
6165 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
6167 rtl_init_rxcfg(tp);
6169 rtl_irq_disable(tp);
6171 rtl_hw_reset(tp);
6173 rtl_ack_events(tp, 0xffff);
6181 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6182 tp->cp_cmd |= RxVlan;
6184 rtl_init_mdio_ops(tp);
6185 rtl_init_pll_power_ops(tp);
6186 rtl_init_jumbo_ops(tp);
6188 rtl8169_print_mac_version(tp);
6190 chipset = tp->mac_version;
6191 tp->txd_version = rtl_chip_infos[chipset].txd_version;
6197 tp->features |= RTL_FEATURE_WOL;
6199 tp->features |= RTL_FEATURE_WOL;
6200 tp->features |= rtl_try_msi(tp, cfg);
6203 if (rtl_tbi_enabled(tp)) {
6204 tp->set_speed = rtl8169_set_speed_tbi;
6205 tp->get_settings = rtl8169_gset_tbi;
6206 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
6207 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
6208 tp->link_ok = rtl8169_tbi_link_ok;
6209 tp->do_ioctl = rtl_tbi_ioctl;
6211 tp->set_speed = rtl8169_set_speed_xmii;
6212 tp->get_settings = rtl8169_gset_xmii;
6213 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
6214 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
6215 tp->link_ok = rtl8169_xmii_link_ok;
6216 tp->do_ioctl = rtl_xmii_ioctl;
6219 mutex_init(&tp->wk.mutex);
6229 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
6241 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6248 tp->hw_start = cfg->hw_start;
6249 tp->event_slow = cfg->event_slow;
6251 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
6254 init_timer(&tp->timer);
6255 tp->timer.data = (unsigned long) dev;
6256 tp->timer.function = rtl8169_phy_timer;
6258 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
6266 netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
6270 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
6276 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6277 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6278 tp->mac_version == RTL_GIGA_MAC_VER_31) {
6279 rtl8168_driver_start(tp);
6282 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
6293 netif_napi_del(&tp->napi);
6294 rtl_disable_msi(pdev, tp);