Lines Matching refs:ioaddr
146 #define SMC_SELECT_BANK(x) { outw(x, ioaddr + BANK_SELECT); }
521 unsigned int ioaddr = dev->base_addr;
530 writeb(ioaddr & 0xff, smc->base + MOT_LAN + CISREG_IOBASE_0);
531 writeb((ioaddr >> 8) & 0xff, smc->base + MOT_LAN + CISREG_IOBASE_1);
541 unsigned int ioaddr = dev->base_addr;
549 outw(MOT_EEPROM + i, ioaddr + POINTER);
551 outw((CTL_RELOAD | CTL_EE_SELECT), ioaddr + CONTROL);
555 wait = ((CTL_RELOAD | CTL_STORE) & inw(ioaddr + CONTROL));
562 addr = inw(ioaddr + GENERAL);
766 unsigned int ioaddr = dev->base_addr;
771 if (inw(ioaddr + BANK_SELECT) >> 8 != 0x33) {
773 outw(0, ioaddr + CONTROL);
779 s = inb(ioaddr + CONFIG);
784 outb(s, ioaddr + CONFIG);
787 s = inw(ioaddr + BASE_ADDR);
788 if ((inw(ioaddr + BANK_SELECT) >> 8 == 0x33) &&
791 s = inw(ioaddr + REVISION);
812 unsigned int ioaddr;
886 ioaddr = dev->base_addr;
890 mir = inw(ioaddr + MEMINFO) & 0xff;
893 mcr = ((rev >> 4) > 3) ? inw(ioaddr + MEMCFG) : 0x0200;
896 smc->cfg = inw(ioaddr + CONFIG) & ~CFG_AUI_SELECT;
1034 unsigned int ioaddr = dev->base_addr;
1036 save = inw(ioaddr + BANK_SELECT);
1041 pr_cont(" %04x", inw(ioaddr + i));
1044 outw(save, ioaddr + BANK_SELECT);
1089 unsigned int ioaddr = dev->base_addr;
1092 dev->name, inw(ioaddr + BANK_SELECT));
1099 outw(0, ioaddr + INTERRUPT);
1101 mask_bits(0xff00, ioaddr + RCR);
1102 mask_bits(0xff00, ioaddr + TCR);
1106 outw(CTL_POWERDOWN, ioaddr + CONTROL );
1126 unsigned int ioaddr = dev->base_addr;
1135 packet_no = inw(ioaddr + PNR_ARR) >> 8;
1148 outw(packet_no, ioaddr + PNR_ARR);
1150 outw(PTR_AUTOINC , ioaddr + POINTER);
1161 outw(0, ioaddr + DATA_1);
1162 outw(length + 6, ioaddr + DATA_1);
1163 outsw(ioaddr + DATA_1, buf, length >> 1);
1166 outw((length & 1) ? 0x2000 | buf[length-1] : 0, ioaddr + DATA_1);
1171 (inw(ioaddr + INTERRUPT) & 0xff00),
1172 ioaddr + INTERRUPT);
1175 outw(MC_ENQUEUE , ioaddr + MMU_CMD);
1188 unsigned int ioaddr = dev->base_addr;
1191 inw(ioaddr)&0xff, inw(ioaddr + 2));
1203 unsigned int ioaddr = dev->base_addr;
1211 skb->len, inw(ioaddr + 2));
1239 outw(MC_RESET, ioaddr + MMU_CMD);
1244 outw(MC_ALLOC | num_pages, ioaddr + MMU_CMD);
1246 ir = inw(ioaddr+INTERRUPT);
1249 outw((ir&0xff00) | IM_ALLOC_INT, ioaddr + INTERRUPT);
1258 outw((IM_ALLOC_INT << 8) | (ir & 0xff00), ioaddr + INTERRUPT);
1273 unsigned int ioaddr = dev->base_addr;
1274 int saved_packet = inw(ioaddr + PNR_ARR) & 0xff;
1275 int packet_no = inw(ioaddr + FIFO_PORTS) & 0x7f;
1279 outw(packet_no, ioaddr + PNR_ARR);
1282 outw(PTR_AUTOINC | PTR_READ | 0, ioaddr + POINTER);
1284 tx_status = inw(ioaddr + DATA_1);
1299 outw(inw(ioaddr + TCR) | TCR_ENABLE | smc->duplex, ioaddr + TCR);
1302 outw(MC_FREEPKT, ioaddr + MMU_CMD); /* Free the packet memory. */
1307 outw(saved_packet, ioaddr + PNR_ARR);
1315 unsigned int ioaddr = dev->base_addr;
1319 ephs = inw(ioaddr + EPH);
1323 card_stats = inw(ioaddr + COUNTER);
1334 outw(inw(ioaddr + TCR) | TCR_ENABLE | smc->duplex, ioaddr + TCR);
1338 outw(CTL_AUTO_RELEASE | 0x0000, ioaddr + CONTROL);
1340 ioaddr + CONTROL);
1350 unsigned int ioaddr;
1358 ioaddr = dev->base_addr;
1361 irq, ioaddr);
1365 saved_bank = inw(ioaddr + BANK_SELECT);
1376 saved_pointer = inw(ioaddr + POINTER);
1377 mask = inw(ioaddr + INTERRUPT) >> 8;
1379 outw(0, ioaddr + INTERRUPT);
1382 status = inw(ioaddr + INTERRUPT) & 0xff;
1396 outw(IM_TX_INT, ioaddr + INTERRUPT);
1400 outw(IM_TX_EMPTY_INT, ioaddr + INTERRUPT);
1422 outw(IM_RX_OVRN_INT, ioaddr + INTERRUPT);
1432 outw((mask<<8), ioaddr + INTERRUPT);
1433 outw(saved_pointer, ioaddr + POINTER);
1443 mask_bits(0x00ff, ioaddr-0x10+OSITECH_RESET_ISR);
1444 set_bits(0x0300, ioaddr-0x10+OSITECH_RESET_ISR);
1477 unsigned int ioaddr = dev->base_addr;
1484 if (inw(ioaddr + FIFO_PORTS) & FP_RXEMPTY) {
1490 outw(PTR_READ | PTR_RCV | PTR_AUTOINC, ioaddr + POINTER);
1491 rx_status = inw(ioaddr + DATA_1);
1492 packet_length = inw(ioaddr + DATA_1) & 0x07ff;
1507 outw(MC_RELEASE, ioaddr + MMU_CMD);
1513 insw(ioaddr+DATA_1, skb_put(skb, packet_length),
1533 outw(MC_RELEASE, ioaddr + MMU_CMD);
1549 unsigned int ioaddr = dev->base_addr;
1578 outb(multicast_table[i], ioaddr + MULTICAST0 + i);
1580 outw(rx_cfg_setting, ioaddr + RCR);
1619 unsigned int ioaddr = dev->base_addr;
1622 saved_bank = inw(ioaddr + BANK_SELECT);
1625 outw(smc->cfg | CFG_AUI_SELECT, ioaddr + CONFIG);
1628 set_bits(OSI_AUI_PWR, ioaddr - 0x10 + OSITECH_AUI_PWR);
1631 outw(smc->cfg, ioaddr + CONFIG);
1634 mask_bits(~OSI_AUI_PWR, ioaddr - 0x10 + OSITECH_AUI_PWR);
1642 unsigned int ioaddr = dev->base_addr;
1652 outw(RCR_SOFTRESET, ioaddr + RCR);
1656 outw(RCR_CLEAR, ioaddr + RCR);
1657 outw(TCR_CLEAR, ioaddr + TCR);
1665 ioaddr + CONTROL);
1670 (inw(ioaddr-0x10+OSITECH_AUI_PWR) & 0xff00),
1671 ioaddr - 0x10 + OSITECH_AUI_PWR);
1676 ioaddr + ADDR0 + i);
1680 outw(MC_RESET, ioaddr + MMU_CMD);
1681 outw(0, ioaddr + INTERRUPT);
1686 TCR_ENABLE | TCR_PAD_EN | smc->duplex, ioaddr + TCR);
1706 ioaddr + INTERRUPT);
1719 unsigned int ioaddr = dev->base_addr;
1726 saved_bank = inw(ioaddr + BANK_SELECT);
1735 outw(MC_RESET, ioaddr + MMU_CMD);
1738 i = inw(ioaddr + INTERRUPT);
1740 media = inw(ioaddr + EPH) & EPH_LINK_OK;
1742 media |= (inw(ioaddr + CONFIG) & CFG_AUI_SELECT) ? 2 : 1;
1766 saved_bank = inw(ioaddr + BANK_SELECT);
1792 outw(inw(ioaddr + TCR) | smc->duplex, ioaddr + TCR);
1839 unsigned int ioaddr = dev->base_addr;
1846 return inw(ioaddr + EPH) & EPH_LINK_OK;
1853 unsigned int ioaddr = dev->base_addr;
1859 tmp = inw(ioaddr + CONFIG);
1863 ecmd->phy_address = ioaddr + MGMT;
1866 tmp = inw(ioaddr + TCR);
1875 unsigned int ioaddr = dev->base_addr;
1892 tmp = inw(ioaddr + TCR);
1897 outw(tmp, ioaddr + TCR);
1918 unsigned int ioaddr = dev->base_addr;
1919 u16 saved_bank = inw(ioaddr + BANK_SELECT);
1937 unsigned int ioaddr = dev->base_addr;
1938 u16 saved_bank = inw(ioaddr + BANK_SELECT);
1956 unsigned int ioaddr = dev->base_addr;
1957 u16 saved_bank = inw(ioaddr + BANK_SELECT);
1973 unsigned int ioaddr = dev->base_addr;
1974 u16 saved_bank = inw(ioaddr + BANK_SELECT);
2001 unsigned int ioaddr = dev->base_addr;
2008 saved_bank = inw(ioaddr + BANK_SELECT);