Lines Matching refs:ioaddr
34 static void dwmac1000_core_init(void __iomem *ioaddr)
36 u32 value = readl(ioaddr + GMAC_CONTROL);
38 writel(value, ioaddr + GMAC_CONTROL);
41 writel(0x207, ioaddr + GMAC_INT_MASK);
45 writel(0x0, ioaddr + GMAC_VLAN_TAG);
49 static int dwmac1000_rx_coe_supported(void __iomem *ioaddr)
51 u32 value = readl(ioaddr + GMAC_CONTROL);
54 writel(value, ioaddr + GMAC_CONTROL);
56 value = readl(ioaddr + GMAC_CONTROL);
61 static void dwmac1000_dump_regs(void __iomem *ioaddr)
64 pr_info("\tDWMAC1000 regs (base addr = 0x%p)\n", ioaddr);
69 offset, readl(ioaddr + offset));
73 static void dwmac1000_set_umac_addr(void __iomem *ioaddr, unsigned char *addr,
76 stmmac_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
80 static void dwmac1000_get_umac_addr(void __iomem *ioaddr, unsigned char *addr,
83 stmmac_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
89 void __iomem *ioaddr = (void __iomem *) dev->base_addr;
100 writel(0xffffffff, ioaddr + GMAC_HASH_HIGH);
101 writel(0xffffffff, ioaddr + GMAC_HASH_LOW);
120 writel(mc_filter[0], ioaddr + GMAC_HASH_LOW);
121 writel(mc_filter[1], ioaddr + GMAC_HASH_HIGH);
134 dwmac1000_set_umac_addr(ioaddr, ha->addr, reg);
143 writel(value, ioaddr + GMAC_FRAME_FILTER);
146 "HI 0x%08x, LO 0x%08x\n", readl(ioaddr + GMAC_FRAME_FILTER),
147 readl(ioaddr + GMAC_HASH_HIGH), readl(ioaddr + GMAC_HASH_LOW));
150 static void dwmac1000_flow_ctrl(void __iomem *ioaddr, unsigned int duplex,
170 writel(flow, ioaddr + GMAC_FLOW_CTRL);
173 static void dwmac1000_pmt(void __iomem *ioaddr, unsigned long mode)
186 writel(pmt, ioaddr + GMAC_PMT);
190 static void dwmac1000_irq_status(void __iomem *ioaddr)
192 u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);
197 readl(ioaddr + GMAC_MMC_TX_INTR));
200 readl(ioaddr + GMAC_MMC_RX_INTR));
203 readl(ioaddr + GMAC_MMC_RX_CSUM_OFFLOAD));
208 readl(ioaddr + GMAC_PMT);
224 struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr)
227 u32 hwid = readl(ioaddr + GMAC_VERSION);