Lines Matching refs:ioaddr
35 static int dwmac100_dma_init(void __iomem *ioaddr, int pbl, u32 dma_tx,
38 u32 value = readl(ioaddr + DMA_BUS_MODE);
43 writel(value, ioaddr + DMA_BUS_MODE);
46 if (!(readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET))
55 ioaddr + DMA_BUS_MODE);
58 writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA);
62 writel(dma_tx, ioaddr + DMA_TX_BASE_ADDR);
63 writel(dma_rx, ioaddr + DMA_RCV_BASE_ADDR);
71 static void dwmac100_dma_operation_mode(void __iomem *ioaddr, int txmode,
74 u32 csr6 = readl(ioaddr + DMA_CONTROL);
83 writel(csr6, ioaddr + DMA_CONTROL);
86 static void dwmac100_dump_dma_regs(void __iomem *ioaddr)
94 readl(ioaddr + DMA_BUS_MODE + i * 4));
96 DMA_CUR_TX_BUF_ADDR, readl(ioaddr + DMA_CUR_TX_BUF_ADDR));
98 DMA_CUR_RX_BUF_ADDR, readl(ioaddr + DMA_CUR_RX_BUF_ADDR));
104 void __iomem *ioaddr)
107 u32 csr8 = readl(ioaddr + DMA_MISSED_FRAME_CTR);