Lines Matching refs:port
59 * Read from port 'port' register 'reg', where the registers
62 static u16 pm3386_port_reg_read(int port, int _reg, int spacing)
67 if (port & 1)
70 return pm3386_reg_read(port >> 1, reg);
74 * Write to port 'port' register 'reg', where the registers
77 static void pm3386_port_reg_write(int port, int _reg, int spacing, u16 value)
82 if (port & 1)
85 pm3386_reg_write(port >> 1, reg, value);
147 void pm3386_init_port(int port)
149 int pm = port >> 1;
155 if (pm3386_port_reg_read(port, 0x30a, 0x100) == 0x0000 &&
156 (pm3386_port_reg_read(port, 0x309, 0x100) & 0xff00) == 0x5000) {
159 temp[0] = pm3386_port_reg_read(port, 0x308, 0x100);
160 temp[1] = pm3386_port_reg_read(port, 0x309, 0x100);
161 temp[2] = pm3386_port_reg_read(port, 0x30a, 0x100);
162 pm3386_port_reg_write(port, 0x308, 0x100, swaph(temp[2]));
163 pm3386_port_reg_write(port, 0x309, 0x100, swaph(temp[1]));
164 pm3386_port_reg_write(port, 0x30a, 0x100, swaph(temp[0]));
172 pm3386_port_reg_write(port, 0x708, 0x10, 0xd055);
174 pm3386_port_reg_write(port, 0x708, 0x10, 0x5055);
180 pm3386_port_reg_write(port, 0x122, 0x20, 0x0002);
195 pm3386_port_reg_write(port, 0x221, 0x20, 0x0007);
201 pm3386_reg_write(pm, 0x203, 0x000d & ~(4 << (port & 1)));
211 pm3386_port_reg_write(port, 0x302, 0x100, 0x0113);
216 pm3386_port_reg_write(port, 0x301, 0x100, 0x8000);
217 pm3386_port_reg_write(port, 0x301, 0x100, 0x0000);
222 pm3386_port_reg_write(port, 0x306, 0x100, 0x0100);
227 pm3386_port_reg_write(port, 0x310, 0x100, 9018);
232 pm3386_port_reg_write(port, 0x336, 0x100, 9018);
239 pm3386_port_reg_write(port, 0x31c, 0x100, 0x0020);
244 pm3386_port_reg_write(port, 0x318, 0x100, 0x0003);
245 pm3386_port_reg_write(port, 0x318, 0x100, 0x0002);
248 void pm3386_get_mac(int port, u8 *mac)
252 temp = pm3386_port_reg_read(port, 0x308, 0x100);
256 temp = pm3386_port_reg_read(port, 0x309, 0x100);
260 temp = pm3386_port_reg_read(port, 0x30a, 0x100);
265 void pm3386_set_mac(int port, u8 *mac)
267 pm3386_port_reg_write(port, 0x308, 0x100, (mac[1] << 8) | mac[0]);
268 pm3386_port_reg_write(port, 0x309, 0x100, (mac[3] << 8) | mac[2]);
269 pm3386_port_reg_write(port, 0x30a, 0x100, (mac[5] << 8) | mac[4]);
272 static u32 pm3386_get_stat(int port, u16 base)
276 value = pm3386_port_reg_read(port, base, 0x100);
277 value |= pm3386_port_reg_read(port, base + 1, 0x100) << 16;
282 void pm3386_get_stats(int port, struct net_device_stats *stats)
287 pm3386_port_reg_write(port, 0x500, 0x100, 0x0001);
288 while (pm3386_port_reg_read(port, 0x500, 0x100) & 0x0001)
293 stats->rx_packets = pm3386_get_stat(port, 0x510);
294 stats->tx_packets = pm3386_get_stat(port, 0x590);
295 stats->rx_bytes = pm3386_get_stat(port, 0x514);
296 stats->tx_bytes = pm3386_get_stat(port, 0x594);
300 void pm3386_set_carrier(int port, int state)
302 pm3386_port_reg_write(port, 0x703, 0x10, state ? 0x1001 : 0x0000);
305 int pm3386_is_link_up(int port)
309 temp = pm3386_port_reg_read(port, 0x31a, 0x100);
310 temp = pm3386_port_reg_read(port, 0x31a, 0x100);
315 void pm3386_enable_rx(int port)
319 temp = pm3386_port_reg_read(port, 0x303, 0x100);
321 pm3386_port_reg_write(port, 0x303, 0x100, temp);
324 void pm3386_disable_rx(int port)
328 temp = pm3386_port_reg_read(port, 0x303, 0x100);
330 pm3386_port_reg_write(port, 0x303, 0x100, temp);
333 void pm3386_enable_tx(int port)
337 temp = pm3386_port_reg_read(port, 0x303, 0x100);
339 pm3386_port_reg_write(port, 0x303, 0x100, temp);
342 void pm3386_disable_tx(int port)
346 temp = pm3386_port_reg_read(port, 0x303, 0x100);
348 pm3386_port_reg_write(port, 0x303, 0x100, temp);