Lines Matching refs:ti
329 struct tok_info *ti = netdev_priv(dev);
330 iounmap(ti->mmio);
331 iounmap(ti->sram_virt);
386 struct tok_info *ti = netdev_priv(dev);
430 t_mmio = ti->mmio; /*BMS to get virtual address */
431 irq = ti->irq; /*BMS to display the irq! */
483 ti->mmio = t_mmio;
491 ti->turbo = 1;
495 ti->readlog_pending = 0;
496 init_waitqueue_head(&ti->wait_for_reset);
508 ti->adapter_int_enable = PIOaddr + ADAPTINTREL;
515 ti->global_int_enable = 0;
516 ti->adapter_int_enable = 0;
517 ti->sram_phys=(__u32)(inb(PIOaddr+ADAPTRESETREL) & 0xfe) << 12;
528 while (!readb(ti->mmio + ACA_OFFSET + ACA_RW + RRR_EVEN)){
534 ti->sram_phys =
535 ((__u32)readb(ti->mmio+ACA_OFFSET+ACA_RW+RRR_EVEN)<<12);
536 ti->adapter_int_enable = PIOaddr + ADAPTINTREL;
543 printk(", sram_phys=0x%x", ti->sram_phys);
545 DPRINTK(", ti->mmio=%p", ti->mmio);
555 temp = readb(ti->mmio + AIP + i) & 0x0f;
556 ti->hw_address[j] = temp;
559 ti->hw_address[j]+ (ti->hw_address[j - 1] << 4);
563 ti->adapter_type = readb(ti->mmio + AIPADAPTYPE);
566 ti->data_rate = readb(ti->mmio + AIPDATARATE);
569 ti->token_release = readb(ti->mmio + AIPEARLYTOKEN);
572 if (ti->turbo) {
573 ti->avail_shared_ram=127;
575 ti->avail_shared_ram = get_sram_size(ti);/*in 512 byte units */
579 ti->shared_ram_paging = readb(ti->mmio + AIPSHRAMPAGE);
582 switch (readb(ti->mmio + AIP4MBDHB)) {
583 case 0xe: ti->dhb_size4mb = 4096; break;
584 case 0xd: ti->dhb_size4mb = 4464; break;
585 default: ti->dhb_size4mb = 2048; break;
589 switch (readb(ti->mmio + AIP16MBDHB)) {
590 case 0xe: ti->dhb_size16mb = 4096; break;
591 case 0xd: ti->dhb_size16mb = 8192; break;
592 case 0xc: ti->dhb_size16mb = 16384; break;
593 case 0xb: ti->dhb_size16mb = 17960; break;
594 default: ti->dhb_size16mb = 2048; break;
608 ti->mapped_ram_size= /*sixteen to onehundredtwentyeight 512byte blocks*/
609 1<< ((readb(ti->mmio+ACA_OFFSET+ACA_RW+RRR_ODD) >> 2 & 0x03) + 4);
610 ti->page_mask = 0;
611 if (ti->turbo) ti->page_mask=0xf0;
612 else if (ti->shared_ram_paging == 0xf); /* No paging in adapter */
618 switch (ti->shared_ram_paging) {
622 ti->page_mask = (ti->mapped_ram_size == 32) ? 0xc0 : 0;
626 ti->page_mask = (ti->mapped_ram_size == 64) ? 0x80 : 0;
630 switch (ti->mapped_ram_size) {
632 ti->page_mask = 0xc0;
636 ti->page_mask = 0x80;
643 ti->shared_ram_paging);
653 ti->shared_ram_paging, ti->mapped_ram_size / 2,
654 ti->avail_shared_ram / 2, ti->page_mask);
666 rrr_32=readb(ti->mmio+ACA_OFFSET+ACA_RW+RRR_ODD) >> 2 & 0x03;
669 chk_base = new_base + (ti->mapped_ram_size << 9);
677 ti->sram_base = new_base >> 12;
681 else ti->sram_base = ti->sram_phys >> 12;
705 channel_def[cardpresent - 1], adapter_def(ti->adapter_type));
707 irq, PIOaddr, ti->mapped_ram_size / 2);
709 if (ti->page_mask)
712 ((ti->page_mask^0xff)+1) >>2, ti->avail_shared_ram / 2);
714 DPRINTK("Shared RAM paging disabled. ti->page_mask %x\n",
715 ti->page_mask);
723 if (!ti->page_mask) {
724 ti->avail_shared_ram=
725 min(ti->mapped_ram_size,ti->avail_shared_ram);
728 switch (ti->avail_shared_ram) {
730 ti->dhb_size4mb = min(ti->dhb_size4mb, (unsigned short)2048);
731 ti->rbuf_len4 = 1032;
732 ti->rbuf_cnt4=2;
733 ti->dhb_size16mb = min(ti->dhb_size16mb, (unsigned short)2048);
734 ti->rbuf_len16 = 1032;
735 ti->rbuf_cnt16=2;
738 ti->dhb_size4mb = min(ti->dhb_size4mb, (unsigned short)4464);
739 ti->rbuf_len4 = 1032;
740 ti->rbuf_cnt4=4;
741 ti->dhb_size16mb = min(ti->dhb_size16mb, (unsigned short)4096);
742 ti->rbuf_len16 = 1032; /*1024 usable */
743 ti->rbuf_cnt16=4;
746 ti->dhb_size4mb = min(ti->dhb_size4mb, (unsigned short)4464);
747 ti->rbuf_len4 = 1032;
748 ti->rbuf_cnt4=6;
749 ti->dhb_size16mb = min(ti->dhb_size16mb, (unsigned short)10240);
750 ti->rbuf_len16 = 1032;
751 ti->rbuf_cnt16=6;
754 ti->dhb_size4mb = min(ti->dhb_size4mb, (unsigned short)4464);
755 ti->rbuf_len4 = 1032;
756 ti->rbuf_cnt4=6;
757 ti->dhb_size16mb = min(ti->dhb_size16mb, (unsigned short)16384);
758 ti->rbuf_len16 = 1032;
759 ti->rbuf_cnt16=16;
762 ti->dhb_size4mb = min(ti->dhb_size4mb, (unsigned short)4464);
763 ti->rbuf_len4 = 1032;
764 ti->rbuf_cnt4=6;
765 ti->dhb_size16mb = min(ti->dhb_size16mb, (unsigned short)17960);
766 ti->rbuf_len16 = 1032;
767 ti->rbuf_cnt16=16;
770 ti->dhb_size4mb = 2048;
771 ti->rbuf_len4 = 1032;
772 ti->rbuf_cnt4=2;
773 ti->dhb_size16mb = 2048;
774 ti->rbuf_len16 = 1032;
775 ti->rbuf_cnt16=2;
779 ti->rbuf_cnt<x> = (ti->avail_shared_ram * BLOCKSZ - ADAPT_PRIVATE -
781 DLC_MAX_STA * STALENGTH - ti->dhb_size<x>mb * NUM_DHB -
782 SRBLENGTH - ASBLENGTH) / ti->rbuf_len<x>;
784 ti->maxmtu16 = (ti->rbuf_len16 - 8) * ti->rbuf_cnt16 - TR_HLEN;
785 ti->maxmtu4 = (ti->rbuf_len4 - 8) * ti->rbuf_cnt4 - TR_HLEN;
788 ti->maxmtu16, ti->maxmtu4);
791 dev->mem_start = ti->sram_base << 12;
792 dev->mem_end = dev->mem_start + (ti->mapped_ram_size << 9) - 1;
832 struct tok_info *ti = netdev_priv(dev);
834 SET_PAGE(ti->srb_page);
835 ti->open_failure = NO ;
845 struct tok_info *ti;
850 ti = netdev_priv(dev);
852 ti->do_tok_int = FIRST_INT;
854 writeb(~INT_ENABLE, ti->mmio + ACA_OFFSET + ACA_RESET + ISRP_EVEN);
861 if (ti->page_mask)
862 writeb(SRPR_ENABLE_PAGING,ti->mmio+ACA_OFFSET+ACA_RW+SRPR_EVEN);
864 writeb(INT_ENABLE, ti->mmio + ACA_OFFSET + ACA_SET + ISRP_EVEN);
865 i = sleep_on_timeout(&ti->wait_for_reset, 4 * HZ);
872 struct tok_info *ti = netdev_priv(dev);
876 if (ti->open_failure == YES) {
881 ti->open_status = CLOSED; /* CLOSED or OPEN */
882 ti->sap_status = CLOSED; /* CLOSED or OPEN */
883 ti->open_failure = NO; /* NO or YES */
884 ti->open_mode = MANUAL; /* MANUAL or AUTOMATIC */
886 ti->sram_phys &= ~1; /* to reverse what we do in tok_close */
888 spin_lock_init(&ti->lock);
889 init_timer(&ti->tr_timer);
896 i= interruptible_sleep_on_timeout(&ti->wait_for_reset, 25 * HZ);
900 if (ti->open_status == OPEN && ti->sap_status==OPEN) {
928 struct tok_info *ti;
931 ti = netdev_priv(dev);
932 SET_PAGE(ti->init_srb_page);
933 writeb(~SRB_RESP_INT, ti->mmio + ACA_OFFSET + ACA_RESET + ISRP_ODD);
935 writeb(0, ti->init_srb + i);
936 writeb(DIR_OPEN_ADAPTER, ti->init_srb + COMMAND_OFST);
937 writew(htons(OPEN_PASS_BCON_MAC), ti->init_srb + OPEN_OPTIONS_OFST);
938 if (ti->ring_speed == 16) {
939 writew(htons(ti->dhb_size16mb), ti->init_srb + DHB_LENGTH_OFST);
940 writew(htons(ti->rbuf_cnt16), ti->init_srb + NUM_RCV_BUF_OFST);
941 writew(htons(ti->rbuf_len16), ti->init_srb + RCV_BUF_LEN_OFST);
943 writew(htons(ti->dhb_size4mb), ti->init_srb + DHB_LENGTH_OFST);
944 writew(htons(ti->rbuf_cnt4), ti->init_srb + NUM_RCV_BUF_OFST);
945 writew(htons(ti->rbuf_len4), ti->init_srb + RCV_BUF_LEN_OFST);
947 writeb(NUM_DHB, /* always 2 */ ti->init_srb + NUM_DHB_OFST);
948 writeb(DLC_MAX_SAP, ti->init_srb + DLC_MAX_SAP_OFST);
949 writeb(DLC_MAX_STA, ti->init_srb + DLC_MAX_STA_OFST);
950 ti->srb = ti->init_srb; /* We use this one in the interrupt handler */
951 ti->srb_page = ti->init_srb_page;
953 readb(ti->init_srb + NUM_DHB_OFST),
954 ntohs(readw(ti->init_srb + DHB_LENGTH_OFST)),
955 ntohs(readw(ti->init_srb + NUM_RCV_BUF_OFST)),
956 ntohs(readw(ti->init_srb + RCV_BUF_LEN_OFST)));
957 writeb(INT_ENABLE, ti->mmio + ACA_OFFSET + ACA_SET + ISRP_EVEN);
958 writeb(CMD_IN_SRB, ti->mmio + ACA_OFFSET + ACA_SET + ISRA_ODD);
966 struct tok_info *ti = netdev_priv(dev);
968 SET_PAGE(ti->srb_page);
970 writeb(0, ti->srb + i);
977 writeb(DLC_OPEN_SAP, ti->srb + COMMAND_OFST);
978 writew(htons(MAX_I_FIELD), ti->srb + MAX_I_FIELD_OFST);
979 writeb(SAP_OPEN_IND_SAP | SAP_OPEN_PRIORITY, ti->srb+ SAP_OPTIONS_OFST);
980 writeb(SAP_OPEN_STATION_CNT, ti->srb + STATION_COUNT_OFST);
981 writeb(type, ti->srb + SAP_VALUE_OFST);
982 writeb(CMD_IN_SRB, ti->mmio + ACA_OFFSET + ACA_SET + ISRA_ODD);
990 struct tok_info *ti = netdev_priv(dev);
998 if (/*BMSHELPdev->start == 0 ||*/ ti->open_status != OPEN) return;
1006 SET_PAGE(ti->srb_page);
1008 writeb(0, ti->srb + i);
1012 writeb(DIR_SET_FUNC_ADDR, ti->srb + COMMAND_OFST);
1014 writeb(address[i], ti->srb + FUNCT_ADDRESS_OFST + i);
1015 writeb(CMD_IN_SRB, ti->mmio + ACA_OFFSET + ACA_SET + ISRA_ODD);
1030 struct tok_info *ti;
1032 ti = netdev_priv(dev);
1037 spin_lock_irqsave(&(ti->lock), flags);
1040 ti->current_skb = skb;
1041 SET_PAGE(ti->srb_page);
1042 writeb(XMIT_UI_FRAME, ti->srb + COMMAND_OFST);
1043 writew(ti->exsap_station_id, ti->srb + STATION_ID_OFST);
1044 writeb(CMD_IN_SRB, ti->mmio + ACA_OFFSET + ACA_SET + ISRA_ODD);
1045 spin_unlock_irqrestore(&(ti->lock), flags);
1053 struct tok_info *ti = netdev_priv(dev);
1057 del_timer_sync(&ti->tr_timer);
1059 ti->sram_phys |= 1;
1060 ti->open_status = CLOSED;
1085 static void __iomem *map_address(struct tok_info *ti, unsigned index, __u8 *page)
1087 if (ti->page_mask) {
1088 *page = (index >> 8) & ti->page_mask;
1089 index &= ~(ti->page_mask << 8);
1091 return ti->sram_virt + index;
1096 struct tok_info *ti = netdev_priv(dev);
1100 ti->srb = map_address(ti,
1101 ntohs(readw(ti->init_srb + SRB_ADDRESS_OFST)),
1102 &ti->srb_page);
1103 ti->ssb = map_address(ti,
1104 ntohs(readw(ti->init_srb + SSB_ADDRESS_OFST)),
1105 &ti->ssb_page);
1106 ti->arb = map_address(ti,
1107 ntohs(readw(ti->init_srb + ARB_ADDRESS_OFST)),
1108 &ti->arb_page);
1109 ti->asb = map_address(ti,
1110 ntohs(readw(ti->init_srb + ASB_ADDRESS_OFST)),
1111 &ti->asb_page);
1112 ti->current_skb = NULL;
1113 ret_code = readb(ti->init_srb + RETCODE_OFST);
1114 err = ntohs(readw(ti->init_srb + OPEN_ERROR_CODE_OFST));
1116 ti->open_status = OPEN; /* TR adapter is now available */
1117 if (ti->open_mode == AUTOMATIC) {
1120 writeb(~SRB_RESP_INT, ti->mmio+ACA_OFFSET+ACA_RESET+ISRP_ODD);
1124 ti->open_failure = YES;
1127 if (!ti->auto_speedsave) {
1131 ti->open_action = FAIL;
1160 if (ti->open_action != FAIL) {
1161 if (ti->open_mode==AUTOMATIC){
1162 ti->open_action = REOPEN;
1163 ibmtr_reset_timer(&(ti->tr_timer), dev);
1166 wake_up(&ti->wait_for_reset);
1178 struct tok_info *ti;
1188 ti = netdev_priv(dev);
1189 if (ti->sram_phys & 1)
1191 spin_lock(&(ti->lock));
1193 save_srpr = readb(ti->mmio + ACA_OFFSET + ACA_RW + SRPR_EVEN);
1197 writeb((~INT_ENABLE), ti->mmio + ACA_OFFSET + ACA_RESET + ISRP_EVEN);
1200 if (ti->adapter_int_enable)
1201 outb(0, ti->adapter_int_enable);
1203 outb(0, ti->global_int_enable);
1204 if (ti->do_tok_int == FIRST_INT){
1207 writeb(save_srpr, ti->mmio + ACA_OFFSET + ACA_RW + SRPR_EVEN);
1209 spin_unlock(&(ti->lock));
1214 status = readb(ti->mmio + ACA_OFFSET + ACA_RW + ISRP_ODD);
1215 /*BMSstatus_even = readb (ti->mmio + ACA_OFFSET + ACA_RW + ISRP_EVEN) */
1223 check_reason = map_address(ti,
1224 ntohs(readw(ti->mmio+ ACA_OFFSET+ACA_RW + WWCR_EVEN)),
1233 writeb(~ADAP_CHK_INT, ti->mmio+ ACA_OFFSET+ACA_RESET+ ISRP_ODD);
1234 status = readb(ti->mmio + ACA_OFFSET + ACA_RW + ISRA_EVEN);
1236 ti->open_status = CLOSED;
1237 ti->sap_status = CLOSED;
1238 ti->open_mode = AUTOMATIC;
1241 ti->open_action = RESTART;
1243 ibmtr_reset_timer(&(ti->tr_timer), dev);/*BMS try to reopen*/
1244 spin_unlock(&(ti->lock));
1247 if (readb(ti->mmio + ACA_OFFSET + ACA_RW + ISRP_EVEN)
1250 (int)readb(ti->mmio+ ACA_OFFSET + ACA_RW + ISRP_EVEN));
1252 ti->mmio + ACA_OFFSET + ACA_RESET + ISRP_EVEN);
1253 status= readb(ti->mmio+ ACA_OFFSET + ACA_RW + ISRA_EVEN);/*BMS*/
1255 writeb(INT_ENABLE, ti->mmio + ACA_OFFSET + ACA_SET + ISRP_EVEN);
1257 writeb(save_srpr, ti->mmio + ACA_OFFSET + ACA_RW + SRPR_EVEN);
1259 spin_unlock(&(ti->lock));
1263 SET_PAGE(ti->srb_page);
1266 readb(ti->srb), readb(ti->srb + RETCODE_OFST));
1268 switch (readb(ti->srb)) { /* SRB command check */
1271 xmit_ret_code = readb(ti->srb + RETCODE_OFST);
1275 if (ti->current_skb) {
1276 dev_kfree_skb_irq(ti->current_skb);
1277 ti->current_skb = NULL;
1281 if (ti->readlog_pending)
1288 xmit_ret_code = readb(ti->srb + RETCODE_OFST);
1292 if (ti->current_skb) {
1293 dev_kfree_skb_irq(ti->current_skb);
1294 ti->current_skb = NULL;
1297 if (ti->readlog_pending)
1305 if (readb(ti->srb + RETCODE_OFST)) {
1308 (int) readb(ti->srb + RETCODE_OFST));
1309 ti->open_action = REOPEN;
1310 ibmtr_reset_timer(&(ti->tr_timer), dev);
1313 ti->exsap_station_id = readw(ti->srb + STATION_ID_OFST);
1314 ti->sap_status = OPEN;/* TR adapter is now available */
1315 if (ti->open_mode==MANUAL){
1316 wake_up(&ti->wait_for_reset);
1327 if (readb(ti->srb + RETCODE_OFST))
1329 (int) readb(ti->srb + COMMAND_OFST),
1330 (int) readb(ti->srb + RETCODE_OFST));
1333 if (readb(ti->srb + RETCODE_OFST)){
1335 (int) readb(ti->srb + RETCODE_OFST));
1358 (int) readb(ti->srb + LINE_ERRORS_OFST),
1359 (int) readb(ti->srb + INTERNAL_ERRORS_OFST),
1360 (int) readb(ti->srb + BURST_ERRORS_OFST),
1361 (int) readb(ti->srb + AC_ERRORS_OFST),
1362 (int) readb(ti->srb + ABORT_DELIMITERS_OFST),
1363 (int) readb(ti->srb + LOST_FRAMES_OFST),
1364 (int) readb(ti->srb + RECV_CONGEST_COUNT_OFST),
1365 (int) readb(ti->srb + FRAME_COPIED_ERRORS_OFST),
1366 (int) readb(ti->srb + FREQUENCY_ERRORS_OFST),
1367 (int) readb(ti->srb + TOKEN_ERRORS_OFST));
1373 (int) readb(ti->srb));
1375 writeb(~SRB_RESP_INT, ti->mmio+ ACA_OFFSET+ACA_RESET+ ISRP_ODD);
1378 SET_PAGE(ti->asb_page);
1380 DPRINTK("ASB resp: cmd=%02X\n", readb(ti->asb));
1383 switch (readb(ti->asb)) { /* ASB command check */
1390 (int) readb(ti->asb));
1392 if (readb(ti->asb + 2) != 0xff) /* checks ret_code */
1394 (int) readb(ti->asb + 2), (int) readb(ti->asb));
1395 writeb(~ASB_FREE_INT, ti->mmio+ ACA_OFFSET+ACA_RESET+ ISRP_ODD);
1402 SET_PAGE(ti->arb_page);
1404 DPRINTK("ARB resp: cmd=%02X\n", readb(ti->arb));
1407 switch (readb(ti->arb)) { /* ARB command check */
1410 ntohs(readw(ti->arb + STATUS_OFST)),
1411 ntohs(readw(ti->arb+ STATION_ID_OFST)));
1418 ring_status= ntohs(readw(ti->arb + NETW_STATUS_OFST));
1434 ti->open_mode = AUTOMATIC;
1435 ti->open_status = CLOSED; /*12/2000 BMS*/
1436 ti->open_action = REOPEN;
1437 ibmtr_reset_timer(&(ti->tr_timer), dev);
1440 ti->readlog_pending = 1;
1451 (int) readb(ti->arb));
1454 writeb(~ARB_CMD_INT, ti->mmio+ ACA_OFFSET+ACA_RESET + ISRP_ODD);
1455 writeb(ARB_FREE, ti->mmio + ACA_OFFSET + ACA_SET + ISRA_ODD);
1459 SET_PAGE(ti->ssb_page);
1462 readb(ti->ssb), readb(ti->ssb + 2));
1465 switch (readb(ti->ssb)) { /* SSB command check */
1468 retcode = readb(ti->ssb + 2);
1472 (int)retcode, (int)readb(ti->ssb + 6));
1478 (int) readb(ti->ssb + 2));
1481 (int) readb(ti->ssb));
1483 writeb(~SSB_RESP_INT, ti->mmio+ ACA_OFFSET+ACA_RESET+ ISRP_ODD);
1484 writeb(SSB_FREE, ti->mmio + ACA_OFFSET + ACA_SET + ISRA_ODD);
1487 writeb(save_srpr, ti->mmio + ACA_OFFSET + ACA_RW + SRPR_EVEN);
1489 writeb(INT_ENABLE, ti->mmio + ACA_OFFSET + ACA_SET + ISRP_EVEN);
1490 spin_unlock(&(ti->lock));
1504 struct tok_info *ti;
1507 ti = netdev_priv(dev);
1509 ti->do_tok_int = NOT_FIRST;
1512 writeb(ti->sram_base, ti->mmio + ACA_OFFSET + ACA_RW + RRR_EVEN);
1514 ti->sram_virt = ioremap(((__u32)ti->sram_base << 12), ti->avail_shared_ram);
1516 ti->init_srb = map_address(ti,
1517 ntohs(readw(ti->mmio + ACA_OFFSET + WRBR_EVEN)),
1518 &ti->init_srb_page);
1519 if (ti->page_mask && ti->avail_shared_ram == 127) {
1523 last_512 = map_address(ti, 0xfe00, &last_512_page);
1529 SET_PAGE(ti->init_srb_page);
1535 DPRINTK("ti->init_srb_page=0x%x\n", ti->init_srb_page);
1536 DPRINTK("init_srb(%p):", ti->init_srb );
1538 printk("%02X ", (int) readb(ti->init_srb + i));
1543 hw_encoded_addr = readw(ti->init_srb + ENCODED_ADDRESS_OFST);
1546 readb(ti->init_srb+offsetof(struct srb_init_response,init_status));
1548 ti->ring_speed = init_status & 0x01 ? 16 : 4;
1550 ti->ring_speed, (unsigned int)dev->mem_start);
1551 ti->auto_speedsave = (readb(ti->init_srb+INIT_STATUS_2_OFST) & 4) != 0;
1553 if (ti->open_mode == MANUAL) wake_up(&ti->wait_for_reset);
1569 struct tok_info *ti = netdev_priv(dev);
1570 struct trh_hdr *trhdr = (struct trh_hdr *) ti->current_skb->data;
1581 SET_PAGE(ti->asb_page);
1583 if (readb(ti->asb+RETCODE_OFST) != 0xFF) DPRINTK("ASB not free !!!\n");
1589 SET_PAGE(ti->arb_page);
1590 dhb=dhb_base=ntohs(readw(ti->arb + DHB_ADDRESS_OFST));
1591 if (ti->page_mask) {
1592 dhb_page = (dhb_base >> 8) & ti->page_mask;
1593 dhb=dhb_base & ~(ti->page_mask << 8);
1595 dhbuf = ti->sram_virt + dhb;
1604 llc = (struct trllc *) (ti->current_skb->data + hdr_len);
1607 SET_PAGE(ti->srb_page);
1608 memcpy_fromio(&xsrb, ti->srb, sizeof(xsrb));
1609 SET_PAGE(ti->asb_page);
1612 writeb(xmit_command, ti->asb + COMMAND_OFST);
1613 writew(xsrb.station_id, ti->asb + STATION_ID_OFST);
1614 writeb(llc_ssap, ti->asb + RSAP_VALUE_OFST);
1615 writeb(xsrb.cmd_corr, ti->asb + CMD_CORRELATE_OFST);
1616 writeb(0, ti->asb + RETCODE_OFST);
1618 writew(htons(0x11), ti->asb + FRAME_LENGTH_OFST);
1619 writeb(0x0e, ti->asb + HEADER_LENGTH_OFST);
1627 writeb(RESP_IN_ASB, ti->mmio + ACA_OFFSET + ACA_SET + ISRA_ODD);
1634 writeb(hdr_len, ti->asb + HEADER_LENGTH_OFST);
1635 writew(htons(ti->current_skb->len), ti->asb + FRAME_LENGTH_OFST);
1636 src_len=ti->current_skb->len;
1640 if (ti->page_mask) {
1641 dhb_page=(dhb >> 8) & ti->page_mask;
1642 dhb=dhb & ~(ti->page_mask << 8);
1645 dhbuf = ti->sram_virt + dhb;
1648 memcpy_toio(dhbuf,&ti->current_skb->data[src_offset],
1656 memcpy_toio(dhbuf, &ti->current_skb->data[src_offset], src_len);
1659 writeb(RESP_IN_ASB, ti->mmio + ACA_OFFSET + ACA_SET + ISRA_ODD);
1660 dev->stats.tx_bytes += ti->current_skb->len;
1661 dev_kfree_skb_irq(ti->current_skb);
1662 ti->current_skb = NULL;
1664 if (ti->readlog_pending)
1683 struct tok_info *ti = netdev_priv(dev);
1697 SET_PAGE(ti->arb_page);
1698 memcpy_fromio(&rarb, ti->arb, sizeof(rarb));
1700 rbuf = map_address(ti, rbuffer, &rbuffer_page);
1702 SET_PAGE(ti->asb_page);
1704 if (readb(ti->asb + RETCODE_OFST) !=0xFF) DPRINTK("ASB not free !!!\n");
1706 writeb(REC_DATA, ti->asb + COMMAND_OFST);
1707 writew(rarb.station_id, ti->asb + STATION_ID_OFST);
1708 writew(rarb.rec_buf_addr, ti->asb + RECEIVE_BUFFER_OFST);
1715 dlc_hdr_len = readb(ti->arb + DLC_HDR_LENGTH_OFST);
1734 SET_PAGE(ti->asb_page);
1735 writeb(DATA_LOST, ti->asb + RETCODE_OFST);
1737 writeb(RESP_IN_ASB, ti->mmio + ACA_OFFSET + ACA_SET + ISRA_ODD);
1772 SET_PAGE(ti->asb_page);
1773 writeb(DATA_LOST, ti->asb + offsetof(struct asb_rec, ret_code));
1774 writeb(RESP_IN_ASB, ti->mmio + ACA_OFFSET + ACA_SET + ISRA_ODD);
1816 rbuf = map_address(ti, rbuffer, &rbuffer_page);
1822 SET_PAGE(ti->asb_page);
1823 writeb(0, ti->asb + offsetof(struct asb_rec, ret_code));
1825 writeb(RESP_IN_ASB, ti->mmio + ACA_OFFSET + ACA_SET + ISRA_ODD);
1854 struct tok_info *ti = netdev_priv(dev);
1856 if ( ti->open_action == RESTART){
1857 ti->do_tok_int = FIRST_INT;
1860 if (ti->page_mask)
1862 ti->mmio + ACA_OFFSET + ACA_RW + SRPR_EVEN);
1865 writeb(INT_ENABLE, ti->mmio + ACA_OFFSET + ACA_SET + ISRP_EVEN);
1874 struct tok_info *ti;
1876 ti = netdev_priv(dev);
1878 ti->readlog_pending = 0;
1879 SET_PAGE(ti->srb_page);
1880 writeb(DIR_READ_LOG, ti->srb);
1881 writeb(INT_ENABLE, ti->mmio + ACA_OFFSET + ACA_SET + ISRP_EVEN);
1882 writeb(CMD_IN_SRB, ti->mmio + ACA_OFFSET + ACA_SET + ISRA_ODD);
1892 struct tok_info *ti = netdev_priv(dev);
1894 if (ti->ring_speed == 16 && mtu > ti->maxmtu16)
1896 if (ti->ring_speed == 4 && mtu > ti->maxmtu4)