Lines Matching refs:queue

33  * basically we have 10 queues to play with. Each queue has a matching
34 * QCU that controls when the queue will get triggered and multiple QCUs
37 * and DCUs allowing us to have different DFS settings for each queue.
39 * When a frame goes into a TX queue, QCU decides when it'll trigger a
41 * it's buffer or -if it's a beacon queue- if it's time to fire up the queue
56 * ath5k_hw_num_tx_pending() - Get number of pending frames for a given queue
58 * @queue: One of enum ath5k_tx_queue_id
61 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue)
64 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
66 /* Return if queue is declared inactive */
67 if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
74 pending = ath5k_hw_reg_read(ah, AR5K_QUEUE_STATUS(queue));
80 if (!pending && AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue))
87 * ath5k_hw_release_tx_queue() - Set a transmit queue inactive
89 * @queue: One of enum ath5k_tx_queue_id
92 ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue)
94 if (WARN_ON(queue >= ah->ah_capabilities.cap_queues.q_tx_num))
97 /* This queue will be skipped in further operations */
98 ah->ah_txq[queue].tqi_type = AR5K_TX_QUEUE_INACTIVE;
100 AR5K_Q_DISABLE_BITS(ah->ah_txq_status, queue);
130 * ath5k_hw_get_tx_queueprops() - Get properties for a transmit queue
132 * @queue: One of enum ath5k_tx_queue_id
136 ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue,
139 memcpy(queue_info, &ah->ah_txq[queue], sizeof(struct ath5k_txq_info));
144 * ath5k_hw_set_tx_queueprops() - Set properties for a transmit queue
146 * @queue: One of enum ath5k_tx_queue_id
149 * Returns 0 on success or -EIO if queue is inactive
152 ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, int queue,
157 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
159 qi = &ah->ah_txq[queue];
193 * ath5k_hw_setup_tx_queue() - Initialize a transmit queue
204 unsigned int queue;
208 * Get queue by type
214 queue = AR5K_TX_QUEUE_ID_NOQCU_DATA;
218 queue = AR5K_TX_QUEUE_ID_NOQCU_BEACON;
226 for (queue = AR5K_TX_QUEUE_ID_DATA_MIN;
227 ah->ah_txq[queue].tqi_type !=
228 AR5K_TX_QUEUE_INACTIVE; queue++) {
230 if (queue > AR5K_TX_QUEUE_ID_DATA_MAX)
235 queue = AR5K_TX_QUEUE_ID_UAPSD;
238 queue = AR5K_TX_QUEUE_ID_BEACON;
241 queue = AR5K_TX_QUEUE_ID_CAB;
249 * Setup internal queue structure
251 memset(&ah->ah_txq[queue], 0, sizeof(struct ath5k_txq_info));
252 ah->ah_txq[queue].tqi_type = queue_type;
256 ret = ath5k_hw_set_tx_queueprops(ah, queue, queue_info);
266 AR5K_Q_ENABLE_BITS(ah->ah_txq_status, queue);
268 return queue;
279 * @queue: One of enum ath5k_tx_queue_id
281 * This function is used when initializing a queue, to set
286 unsigned int queue)
288 /* Single data queue on AR5210 */
290 struct ath5k_txq_info *tq = &ah->ah_txq[queue];
292 if (queue > 0)
315 AR5K_QUEUE_DFS_RETRY_LIMIT(queue));
320 * ath5k_hw_reset_tx_queue() - Initialize a single hw queue
322 * @queue: One of enum ath5k_tx_queue_id
324 * Set DCF properties for the given transmit queue on DCU
325 * and configures all queue-specific parameters.
328 ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue)
330 struct ath5k_txq_info *tq = &ah->ah_txq[queue];
332 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
334 tq = &ah->ah_txq[queue];
336 /* Skip if queue inactive or if we are on AR5210
350 AR5K_QUEUE_DFS_LOCAL_IFS(queue));
353 * Set tx retry limits for this queue
355 ath5k_hw_set_tx_retry_limits(ah, queue);
363 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
368 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
377 AR5K_QUEUE_CBRCFG(queue));
379 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
383 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
392 AR5K_QUEUE_RDYTIMECFG(queue));
398 AR5K_QUEUE_DFS_CHANNEL_TIME(queue));
401 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
408 AR5K_QUEUE_DFS_MISC(queue));
413 AR5K_QUEUE_DFS_MISC(queue));
416 * Set registers by queue type
420 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
425 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
435 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
445 AR5K_QUEUE_RDYTIMECFG(queue));
447 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
453 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
465 * Enable interrupts for this tx queue
469 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txok, queue);
472 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txerr, queue);
475 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txurn, queue);
478 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txdesc, queue);
481 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txeol, queue);
484 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_cbrorn, queue);
487 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_cbrurn, queue);
490 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_qtrig, queue);
493 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_nofrm, queue);
539 /* No queue has TXNOFRM enabled, disable the interrupt
545 AR5K_REG_WRITE_Q(ah, AR5K_QUEUE_QCUMASK(queue), queue);
686 "failed to reset TX queue #%d\n", i);