Lines Matching refs:clock
41 * that don't fit on other places such as clock, sleep and power control
89 * ath5k_hw_htoclock() - Translate usec to hw clock units
93 * Translate usecs to hw clock units based on the current
94 * hw clock rate.
96 * Returns number of clock units
106 * ath5k_hw_clocktoh() - Translate hw clock units to usec
108 * @clock: value in hw clock units
110 * Translate hw clock units to usecs based on the current
111 * hw clock rate.
116 ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock)
119 return clock / common->clockrate;
123 * ath5k_hw_init_core_clock() - Initialize core clock
126 * Initialize core clock parameters (usec, usec32, latencies etc),
134 u32 usec_reg, txlat, rxlat, usec, clock, sclock, txf2txs;
137 * Set core clock frequency
141 clock = 40;
144 clock = 22;
148 clock = 44;
152 /* Use clock multiplier for non-default
156 clock *= 2;
159 clock /= 2;
162 clock /= 4;
168 common->clockrate = clock;
174 usec = clock - 1;
181 clock);
189 /* Remain on 40MHz clock ? */
266 * ath5k_hw_set_sleep_clock() - Setup sleep clock operation
268 * @enable: Enable sleep clock operation (false to disable)
271 * as ref. clock instead of 32/40MHz clock and baseband clocks
326 /* Enable sleep clock operation */
332 /* Disable sleep clock operation and
670 u32 turbo, mode, clock, bus_flags;
675 clock = 0;
747 clock = AR5K_PHY_PLL_RF5112;
750 clock = AR5K_PHY_PLL_RF5111; /*Zero*/
755 clock |= AR5K_PHY_PLL_44MHZ;
778 clock = AR5K_PHY_PLL_40MHZ_5413;
780 clock |= AR5K_PHY_PLL_40MHZ;
799 clock |= (ah->ah_bwmode == AR5K_BWMODE_10MHZ) ?
816 if (ath5k_hw_reg_read(ah, AR5K_PHY_PLL) != clock) {
817 ath5k_hw_reg_write(ah, clock, AR5K_PHY_PLL);
915 /* Clear QCU/DCU clock gating register */
1164 /* Disable sleep clock operation
1312 /* Initialize core clock settings */
1384 * Enable 32KHz clock function for AR5212+ chips