Lines Matching refs:priv
90 struct rtl8180_priv *priv = dev->priv;
96 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->PHY[0], buf | 0x80);
98 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->PHY[0], buf);
99 if (rtl818x_ioread8(priv, &priv->map->PHY[2]) == (data & 0xFF))
106 struct rtl8180_priv *priv = dev->priv;
111 struct rtl8180_rx_desc *entry = &priv->rx_ring[priv->rx_idx];
112 struct sk_buff *skb = priv->rx_buf[priv->rx_idx];
130 pci_unmap_single(priv->pdev,
138 if (priv->r8185) {
145 signal = priv->rf->calc_rssi(agc, sq);
159 priv->rx_buf[priv->rx_idx] = skb;
161 pci_map_single(priv->pdev, skb_tail_pointer(skb),
169 if (priv->rx_idx == 31)
171 priv->rx_idx = (priv->rx_idx + 1) % 32;
177 struct rtl8180_priv *priv = dev->priv;
178 struct rtl8180_tx_ring *ring = &priv->tx_ring[prio];
191 pci_unmap_single(priv->pdev, le32_to_cpu(entry->tx_buf),
213 struct rtl8180_priv *priv = dev->priv;
216 spin_lock(&priv->lock);
217 reg = rtl818x_ioread16(priv, &priv->map->INT_STATUS);
219 spin_unlock(&priv->lock);
223 rtl818x_iowrite16(priv, &priv->map->INT_STATUS, reg);
240 spin_unlock(&priv->lock);
249 struct rtl8180_priv *priv = dev->priv;
261 ring = &priv->tx_ring[prio];
263 mapping = pci_map_single(priv->pdev, skb->data,
271 if (priv->r8185)
285 rts_duration = ieee80211_rts_duration(dev, priv->vif, skb->len,
288 if (!priv->r8185) {
299 spin_lock_irqsave(&priv->lock, flags);
303 priv->seqno += 0x10;
305 hdr->seq_ctrl |= cpu_to_le16(priv->seqno);
323 spin_unlock_irqrestore(&priv->lock, flags);
325 rtl818x_iowrite8(priv, &priv->map->TX_DMA_POLLING, (1 << (prio + 4)));
328 void rtl8180_set_anaparam(struct rtl8180_priv *priv, u32 anaparam)
332 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
333 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
334 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
336 rtl818x_iowrite32(priv, &priv->map->ANAPARAM, anaparam);
337 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
339 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
344 struct rtl8180_priv *priv = dev->priv;
347 rtl818x_iowrite8(priv, &priv->map->CMD, 0);
348 rtl818x_ioread8(priv, &priv->map->CMD);
352 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
353 rtl818x_ioread8(priv, &priv->map->CMD);
355 reg = rtl818x_ioread8(priv, &priv->map->CMD);
358 rtl818x_iowrite8(priv, &priv->map->CMD, RTL818X_CMD_RESET);
359 rtl818x_ioread8(priv, &priv->map->CMD);
363 if (rtl818x_ioread8(priv, &priv->map->CMD) & RTL818X_CMD_RESET) {
368 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_LOAD);
369 rtl818x_ioread8(priv, &priv->map->CMD);
372 if (rtl818x_ioread8(priv, &priv->map->CONFIG3) & (1 << 3)) {
374 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
376 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
377 reg = rtl818x_ioread16(priv, &priv->map->FEMR);
379 rtl818x_iowrite16(priv, &priv->map->FEMR, reg);
382 rtl818x_iowrite8(priv, &priv->map->MSR, 0);
384 if (!priv->r8185)
385 rtl8180_set_anaparam(priv, priv->anaparam);
387 rtl818x_iowrite32(priv, &priv->map->RDSAR, priv->rx_ring_dma);
388 rtl818x_iowrite32(priv, &priv->map->TBDA, priv->tx_ring[3].dma);
389 rtl818x_iowrite32(priv, &priv->map->THPDA, priv->tx_ring[2].dma);
390 rtl818x_iowrite32(priv, &priv->map->TNPDA, priv->tx_ring[1].dma);
391 rtl818x_iowrite32(priv, &priv->map->TLPDA, priv->tx_ring[0].dma);
394 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
395 reg = rtl818x_ioread8(priv, &priv->map->CONFIG2);
396 rtl818x_iowrite8(priv, &priv->map->CONFIG2, reg & ~(1 << 3));
397 if (priv->r8185) {
398 reg = rtl818x_ioread8(priv, &priv->map->CONFIG2);
399 rtl818x_iowrite8(priv, &priv->map->CONFIG2, reg | (1 << 4));
401 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
407 rtl818x_iowrite32(priv, &priv->map->INT_TIMEOUT, 0);
409 if (priv->r8185) {
410 rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0);
411 rtl818x_iowrite8(priv, &priv->map->RATE_FALLBACK, 0x81);
412 rtl818x_iowrite8(priv, &priv->map->RESP_RATE, (8 << 4) | 0);
414 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
417 reg = rtl818x_ioread8(priv, &priv->map->GP_ENABLE);
418 rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, reg & ~(1 << 6));
419 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
420 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
421 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg | (1 << 2));
422 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
424 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x1);
425 rtl818x_iowrite8(priv, &priv->map->SECURITY, 0);
427 rtl818x_iowrite8(priv, &priv->map->PHY_DELAY, 0x6);
428 rtl818x_iowrite8(priv, &priv->map->CARRIER_SENSE_COUNTER, 0x4C);
431 priv->rf->init(dev);
432 if (priv->r8185)
433 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
439 struct rtl8180_priv *priv = dev->priv;
443 priv->rx_ring = pci_alloc_consistent(priv->pdev,
444 sizeof(*priv->rx_ring) * 32,
445 &priv->rx_ring_dma);
447 if (!priv->rx_ring || (unsigned long)priv->rx_ring & 0xFF) {
452 memset(priv->rx_ring, 0, sizeof(*priv->rx_ring) * 32);
453 priv->rx_idx = 0;
458 entry = &priv->rx_ring[i];
462 priv->rx_buf[i] = skb;
464 *mapping = pci_map_single(priv->pdev, skb_tail_pointer(skb),
476 struct rtl8180_priv *priv = dev->priv;
480 struct sk_buff *skb = priv->rx_buf[i];
484 pci_unmap_single(priv->pdev,
490 pci_free_consistent(priv->pdev, sizeof(*priv->rx_ring) * 32,
491 priv->rx_ring, priv->rx_ring_dma);
492 priv->rx_ring = NULL;
498 struct rtl8180_priv *priv = dev->priv;
503 ring = pci_alloc_consistent(priv->pdev, sizeof(*ring) * entries, &dma);
511 priv->tx_ring[prio].desc = ring;
512 priv->tx_ring[prio].dma = dma;
513 priv->tx_ring[prio].idx = 0;
514 priv->tx_ring[prio].entries = entries;
515 skb_queue_head_init(&priv->tx_ring[prio].queue);
526 struct rtl8180_priv *priv = dev->priv;
527 struct rtl8180_tx_ring *ring = &priv->tx_ring[prio];
533 pci_unmap_single(priv->pdev, le32_to_cpu(entry->tx_buf),
539 pci_free_consistent(priv->pdev, sizeof(*ring->desc)*ring->entries,
546 struct rtl8180_priv *priv = dev->priv;
562 rtl818x_iowrite32(priv, &priv->map->RDSAR, priv->rx_ring_dma);
563 rtl818x_iowrite32(priv, &priv->map->TBDA, priv->tx_ring[3].dma);
564 rtl818x_iowrite32(priv, &priv->map->THPDA, priv->tx_ring[2].dma);
565 rtl818x_iowrite32(priv, &priv->map->TNPDA, priv->tx_ring[1].dma);
566 rtl818x_iowrite32(priv, &priv->map->TLPDA, priv->tx_ring[0].dma);
568 ret = request_irq(priv->pdev->irq, rtl8180_interrupt,
575 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
577 rtl818x_iowrite32(priv, &priv->map->MAR[0], ~0);
578 rtl818x_iowrite32(priv, &priv->map->MAR[1], ~0);
588 if (priv->r8185)
591 reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE1)
593 reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE2)
597 priv->rx_conf = reg;
598 rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
600 if (priv->r8185) {
601 reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
604 rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
606 reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
610 rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
613 rtl818x_iowrite8(priv, (u8 __iomem *)priv->map + 0xec, 0x3f);
616 reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
620 if (priv->r8185)
628 rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg);
630 reg = rtl818x_ioread8(priv, &priv->map->CMD);
633 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
640 if (priv->tx_ring[i].desc)
648 struct rtl8180_priv *priv = dev->priv;
652 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
654 reg = rtl818x_ioread8(priv, &priv->map->CMD);
657 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
659 priv->rf->stop(dev);
661 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
662 reg = rtl818x_ioread8(priv, &priv->map->CONFIG4);
663 rtl818x_iowrite8(priv, &priv->map->CONFIG4, reg | RTL818X_CONFIG4_VCOOFF);
664 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
666 free_irq(priv->pdev->irq, dev);
676 struct rtl8180_priv *priv = dev->priv;
678 return rtl818x_ioread32(priv, &priv->map->TSFT[0]) |
679 (u64)(rtl818x_ioread32(priv, &priv->map->TSFT[1])) << 32;
725 struct rtl8180_priv *priv = dev->priv;
731 if (priv->vif)
742 priv->vif = vif;
750 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
751 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->MAC[0],
753 rtl818x_iowrite16(priv, (__le16 __iomem *)&priv->map->MAC[4],
755 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
763 struct rtl8180_priv *priv = dev->priv;
764 priv->vif = NULL;
769 struct rtl8180_priv *priv = dev->priv;
772 priv->rf->set_chan(dev, conf);
782 struct rtl8180_priv *priv = dev->priv;
791 rtl818x_iowrite8(priv, &priv->map->BSSID[i],
801 rtl818x_iowrite8(priv, &priv->map->MSR, reg);
804 if (changed & BSS_CHANGED_ERP_SLOT && priv->rf->conf_erp)
805 priv->rf->conf_erp(dev, info);
828 struct rtl8180_priv *priv = dev->priv;
831 priv->rx_conf ^= RTL818X_RX_CONF_FCS;
833 priv->rx_conf ^= RTL818X_RX_CONF_CTRL;
835 priv->rx_conf ^= RTL818X_RX_CONF_MONITOR;
837 priv->rx_conf |= RTL818X_RX_CONF_MULTICAST;
839 priv->rx_conf &= ~RTL818X_RX_CONF_MULTICAST;
843 if (priv->rx_conf & RTL818X_RX_CONF_FCS)
845 if (priv->rx_conf & RTL818X_RX_CONF_CTRL)
847 if (priv->rx_conf & RTL818X_RX_CONF_MONITOR)
849 if (priv->rx_conf & RTL818X_RX_CONF_MULTICAST)
852 rtl818x_iowrite32(priv, &priv->map->RX_CONF, priv->rx_conf);
871 struct rtl8180_priv *priv = dev->priv;
872 u8 reg = rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
883 struct rtl8180_priv *priv = dev->priv;
895 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, reg);
896 rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
904 struct rtl8180_priv *priv;
950 dev = ieee80211_alloc_hw(sizeof(*priv), &rtl8180_ops);
958 priv = dev->priv;
959 priv->pdev = pdev;
965 priv->map = pci_iomap(pdev, 1, mem_len);
966 if (!priv->map)
967 priv->map = pci_iomap(pdev, 0, io_len);
969 if (!priv->map) {
975 BUILD_BUG_ON(sizeof(priv->channels) != sizeof(rtl818x_channels));
976 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(rtl818x_rates));
978 memcpy(priv->channels, rtl818x_channels, sizeof(rtl818x_channels));
979 memcpy(priv->rates, rtl818x_rates, sizeof(rtl818x_rates));
981 priv->band.band = IEEE80211_BAND_2GHZ;
982 priv->band.channels = priv->channels;
983 priv->band.n_channels = ARRAY_SIZE(rtl818x_channels);
984 priv->band.bitrates = priv->rates;
985 priv->band.n_bitrates = 4;
986 dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
997 reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
1018 priv->r8185 = reg & RTL818X_TX_CONF_R8185_ABC;
1019 if (priv->r8185) {
1020 priv->band.n_bitrates = ARRAY_SIZE(rtl818x_rates);
1027 if (rtl818x_ioread32(priv, &priv->map->RX_CONF) & (1 << 6))
1032 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_PROGRAM);
1033 rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
1043 case 3: priv->rf = &sa2400_rf_ops;
1045 case 4: priv->rf = &max2820_rf_ops;
1047 case 5: priv->rf = &grf5101_rf_ops;
1049 case 9: priv->rf = rtl8180_detect_rf(dev);
1060 if (!priv->rf) {
1067 priv->csthreshold = eeprom_val >> 8;
1068 if (!priv->r8185) {
1071 priv->anaparam = le32_to_cpu(anaparam);
1072 eeprom_93cx6_read(&eeprom, 0x19, &priv->rfparam);
1087 priv->channels[i].hw_value = txpwr & 0xFF;
1088 priv->channels[i + 1].hw_value = txpwr >> 8;
1092 if (priv->r8185) {
1096 priv->channels[i].hw_value |= (txpwr & 0xFF) << 8;
1097 priv->channels[i + 1].hw_value |= txpwr & 0xFF00;
1101 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
1103 spin_lock_init(&priv->lock);
1113 mac_addr, chip_name, priv->rf->name);
1118 iounmap(priv->map);
1133 struct rtl8180_priv *priv;
1140 priv = dev->priv;
1142 pci_iounmap(pdev, priv->map);