Lines Matching refs:base
541 * Saves the length of all base address registers for the
554 u32 base;
588 * IO and memory base lengths
593 pci_bus_read_config_dword (pci_bus, devfn, cloop, &base);
595 if (base) {
596 if (base & 0x01L) {
597 /* IO base
598 * set base = amount of IO space
601 base = base & 0xFFFFFFFE;
602 base = (~base) + 1;
606 /* memory base */
607 base = base & 0xFFFFFFF0;
608 base = (~base) + 1;
613 base = 0x0L;
619 base;
622 } /* End of base register loop */
625 /* Figure out IO and memory base lengths */
629 pci_bus_read_config_dword (pci_bus, devfn, cloop, &base);
632 if (base) {
633 if (base & 0x01L) {
634 /* IO base
635 * base = amount of IO space
638 base = base & 0xFFFFFFFE;
639 base = (~base) + 1;
643 /* memory base
644 * base = amount of memory
647 base = base & 0xFFFFFFF0;
648 base = (~base) + 1;
653 base = 0x0L;
658 func->base_length[(cloop - 0x10) >> 2] = base;
661 } /* End of base register loop */
697 u32 base;
733 bus_node->base = secondary_bus;
739 /* Save IO base and Limit registers */
748 io_node->base = (b_base & 0xF0) << 8;
755 /* Save memory base and Limit registers */
764 mem_node->base = w_base << 16;
771 /* Save prefetchable memory base and Limit registers */
780 p_mem_node->base = w_base << 16;
786 /* Figure out IO and memory base lengths */
792 pci_bus_read_config_dword(pci_bus, devfn, cloop, &base);
794 temp_register = base;
797 if (base) {
798 if (((base & 0x03L) == 0x01)
800 /* IO base
804 temp_register = base & 0xFFFFFFFE;
812 io_node->base =
819 if (((base & 0x0BL) == 0x08)
821 /* prefetchable memory base */
822 temp_register = base & 0xFFFFFFF0;
830 p_mem_node->base = save_base & (~0x0FL);
836 if (((base & 0x0BL) == 0x00)
838 /* prefetchable memory base */
839 temp_register = base & 0xFFFFFFF0;
847 mem_node->base = save_base & (~0x0FL);
855 } /* End of base register loop */
858 /* Figure out IO and memory base lengths */
864 pci_bus_read_config_dword(pci_bus, devfn, cloop, &base);
866 temp_register = base;
869 if (base) {
870 if (((base & 0x03L) == 0x01)
872 /* IO base
876 temp_register = base & 0xFFFFFFFE;
884 io_node->base = save_base & (~0x01L);
890 if (((base & 0x0BL) == 0x08)
892 /* prefetchable memory base */
893 temp_register = base & 0xFFFFFFF0;
901 p_mem_node->base = save_base & (~0x0FL);
907 if (((base & 0x0BL) == 0x00)
909 /* prefetchable memory base */
910 temp_register = base & 0xFFFFFFF0;
918 mem_node->base = save_base & (~0x0FL);
926 } /* End of base register loop */
990 /* Check all the base Address Registers to make sure
1031 u32 base;
1102 /* Figure out IO and memory base lengths */
1106 pci_bus_read_config_dword (pci_bus, devfn, cloop, &base);
1109 if (base) {
1110 if (base & 0x01L) {
1111 /* IO base
1112 * set base = amount of IO
1115 base = base & 0xFFFFFFFE;
1116 base = (~base) + 1;
1120 /* memory base */
1121 base = base & 0xFFFFFFF0;
1122 base = (~base) + 1;
1127 base = 0x0L;
1132 if (func->base_length[(cloop - 0x10) >> 2] != base)
1138 } /* End of base register loop */
1239 dbg("dev|IO base|length|Mem base|length|Pre base|length|PB SB MB\n");
1296 /* If we've got a valid IO base, use it */
1305 io_node->base = io_base;
1308 dbg("found io_node(base, length) = %x, %x\n",
1309 io_node->base, io_node->length);
1320 /* If we've got a valid memory base, use it */
1327 mem_node->base = mem_base << 16;
1331 dbg("found mem_node(base, length) = %x, %x\n",
1332 mem_node->base, mem_node->length);
1343 /* If we've got a valid prefetchable memory base, and
1344 * the base + length isn't greater than 0xFFFF
1352 p_mem_node->base = pre_mem_base << 16;
1355 dbg("found p_mem_node(base, length) = %x, %x\n",
1356 p_mem_node->base, p_mem_node->length);
1377 bus_node->base = secondary_bus;
1379 dbg("found bus_node(base, length) = %x, %x\n",
1380 bus_node->base, bus_node->length);