Lines Matching refs:ctrl
44 static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value)
46 struct pci_dev *dev = ctrl->pcie->port;
50 static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value)
52 struct pci_dev *dev = ctrl->pcie->port;
56 static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value)
58 struct pci_dev *dev = ctrl->pcie->port;
62 static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value)
64 struct pci_dev *dev = ctrl->pcie->port;
73 static void start_int_poll_timer(struct controller *ctrl, int sec);
78 struct controller *ctrl = (struct controller *)data;
81 pcie_isr(0, ctrl);
83 init_timer(&ctrl->poll_timer);
87 start_int_poll_timer(ctrl, pciehp_poll_time);
91 static void start_int_poll_timer(struct controller *ctrl, int sec)
97 ctrl->poll_timer.function = &int_poll_timeout;
98 ctrl->poll_timer.data = (unsigned long)ctrl;
99 ctrl->poll_timer.expires = jiffies + sec * HZ;
100 add_timer(&ctrl->poll_timer);
103 static inline int pciehp_request_irq(struct controller *ctrl)
105 int retval, irq = ctrl->pcie->irq;
109 init_timer(&ctrl->poll_timer);
110 start_int_poll_timer(ctrl, 10);
115 retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl);
117 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
122 static inline void pciehp_free_irq(struct controller *ctrl)
125 del_timer_sync(&ctrl->poll_timer);
127 free_irq(ctrl->pcie->irq, ctrl);
130 static int pcie_poll_cmd(struct controller *ctrl)
135 err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
137 pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC);
143 err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
145 pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC);
152 static void pcie_wait_cmd(struct controller *ctrl, int poll)
159 rc = pcie_poll_cmd(ctrl);
161 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
163 ctrl_dbg(ctrl, "Command not completed in 1000 msec\n");
168 * @ctrl: controller to which the command is issued
172 static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
178 mutex_lock(&ctrl->ctrl_lock);
180 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
182 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
188 if (!ctrl->no_cmd_complete) {
194 ctrl_dbg(ctrl, "CMD_COMPLETED not clear after 1 sec\n");
195 } else if (!NO_CMD_CMPL(ctrl)) {
201 ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Need to "
203 ctrl->no_cmd_complete = 0;
205 ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Maybe "
210 retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl);
212 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
218 ctrl->cmd_busy = 1;
220 retval = pciehp_writew(ctrl, PCI_EXP_SLTCTL, slot_ctrl);
222 ctrl_err(ctrl, "Cannot write to SLOTCTRL register\n");
227 if (!retval && !ctrl->no_cmd_complete) {
237 pcie_wait_cmd(ctrl, poll);
240 mutex_unlock(&ctrl->ctrl_lock);
244 static bool check_link_active(struct controller *ctrl)
249 if (pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status))
255 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
260 static void __pcie_wait_link_active(struct controller *ctrl, bool active)
264 if (check_link_active(ctrl) == active)
269 if (check_link_active(ctrl) == active)
272 ctrl_dbg(ctrl, "Data Link Layer Link Active not %s in 1000 msec\n",
276 static void pcie_wait_link_active(struct controller *ctrl)
278 __pcie_wait_link_active(ctrl, true);
281 static void pcie_wait_link_not_active(struct controller *ctrl)
283 __pcie_wait_link_active(ctrl, false);
312 int pciehp_check_link_status(struct controller *ctrl)
323 if (ctrl->link_active_reporting)
324 pcie_wait_link_active(ctrl);
330 found = pci_bus_check_dev(ctrl->pcie->port->subordinate,
333 retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
335 ctrl_err(ctrl, "Cannot read LNKSTATUS register\n");
339 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
342 ctrl_err(ctrl, "Link Training Error occurs \n");
347 pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);
355 static int __pciehp_link_set(struct controller *ctrl, bool enable)
360 retval = pciehp_readw(ctrl, PCI_EXP_LNKCTL, &lnk_ctrl);
362 ctrl_err(ctrl, "Cannot read LNKCTRL register\n");
371 retval = pciehp_writew(ctrl, PCI_EXP_LNKCTL, lnk_ctrl);
373 ctrl_err(ctrl, "Cannot write LNKCTRL register\n");
376 ctrl_dbg(ctrl, "%s: lnk_ctrl = %x\n", __func__, lnk_ctrl);
381 static int pciehp_link_enable(struct controller *ctrl)
383 return __pciehp_link_set(ctrl, true);
386 static int pciehp_link_disable(struct controller *ctrl)
388 return __pciehp_link_set(ctrl, false);
393 struct controller *ctrl = slot->ctrl;
398 retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl);
400 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
404 ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__,
405 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
432 struct controller *ctrl = slot->ctrl;
437 retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl);
439 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
442 ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__,
443 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
464 struct controller *ctrl = slot->ctrl;
468 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
470 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
480 struct controller *ctrl = slot->ctrl;
484 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
486 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
496 struct controller *ctrl = slot->ctrl;
500 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
502 ctrl_err(ctrl, "Cannot check for power fault\n");
510 struct controller *ctrl = slot->ctrl;
528 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
529 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
530 return pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
535 struct controller *ctrl = slot->ctrl;
541 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
542 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
543 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
548 struct controller *ctrl = slot->ctrl;
554 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
555 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
556 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
561 struct controller *ctrl = slot->ctrl;
567 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
568 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
569 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
574 struct controller *ctrl = slot->ctrl;
581 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
583 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
589 retval = pciehp_writew(ctrl, PCI_EXP_SLTSTA, slot_status);
591 ctrl_err(ctrl,
597 ctrl->power_fault_detected = 0;
601 retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
603 ctrl_err(ctrl, "Write %x command failed!\n", slot_cmd);
606 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
607 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
609 retval = pciehp_link_enable(ctrl);
611 ctrl_err(ctrl, "%s: Can not enable the link!\n", __func__);
618 struct controller *ctrl = slot->ctrl;
624 pciehp_link_disable(ctrl);
626 if (ctrl->link_active_reporting)
627 pcie_wait_link_not_active(ctrl);
633 retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
635 ctrl_err(ctrl, "Write command failed!\n");
638 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
639 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
645 struct controller *ctrl = (struct controller *)dev_id;
646 struct slot *slot = ctrl->slot;
656 if (pciehp_readw(ctrl, PCI_EXP_SLTSTA, &detected)) {
657 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS\n",
669 if (detected && pciehp_writew(ctrl, PCI_EXP_SLTSTA, intr_loc)) {
670 ctrl_err(ctrl, "%s: Cannot write to SLOTSTATUS\n",
676 ctrl_dbg(ctrl, "%s: intr_loc %x\n", __func__, intr_loc);
680 ctrl->cmd_busy = 0;
682 wake_up(&ctrl->queue);
701 if ((intr_loc & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) {
702 ctrl->power_fault_detected = 1;
711 struct controller *ctrl = slot->ctrl;
716 retval = pciehp_readl(ctrl, PCI_EXP_LNKCAP, &lnk_cap);
718 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__);
753 ctrl_dbg(ctrl, "Max link width = %d\n", lnk_wdth);
761 struct controller *ctrl = slot->ctrl;
766 retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
768 ctrl_err(ctrl, "%s: Cannot read LNKSTATUS register\n",
804 ctrl_dbg(ctrl, "Current link width = %d\n", lnk_wdth);
809 int pcie_enable_notification(struct controller *ctrl)
824 if (ATTN_BUTTN(ctrl))
826 if (MRL_SENS(ctrl))
835 if (pcie_write_cmd(ctrl, cmd, mask)) {
836 ctrl_err(ctrl, "Cannot enable software notification\n");
842 static void pcie_disable_notification(struct controller *ctrl)
849 if (pcie_write_cmd(ctrl, 0, mask))
850 ctrl_warn(ctrl, "Cannot disable software notification\n");
853 int pcie_init_notification(struct controller *ctrl)
855 if (pciehp_request_irq(ctrl))
857 if (pcie_enable_notification(ctrl)) {
858 pciehp_free_irq(ctrl);
861 ctrl->notification_enabled = 1;
865 static void pcie_shutdown_notification(struct controller *ctrl)
867 if (ctrl->notification_enabled) {
868 pcie_disable_notification(ctrl);
869 pciehp_free_irq(ctrl);
870 ctrl->notification_enabled = 0;
874 static int pcie_init_slot(struct controller *ctrl)
882 slot->ctrl = ctrl;
885 ctrl->slot = slot;
889 static void pcie_cleanup_slot(struct controller *ctrl)
891 struct slot *slot = ctrl->slot;
897 static inline void dbg_ctrl(struct controller *ctrl)
901 struct pci_dev *pdev = ctrl->pcie->port;
906 ctrl_info(ctrl, "Hotplug Controller:\n");
907 ctrl_info(ctrl, " Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n",
909 ctrl_info(ctrl, " Vendor ID : 0x%04x\n", pdev->vendor);
910 ctrl_info(ctrl, " Device ID : 0x%04x\n", pdev->device);
911 ctrl_info(ctrl, " Subsystem ID : 0x%04x\n",
913 ctrl_info(ctrl, " Subsystem Vendor ID : 0x%04x\n",
915 ctrl_info(ctrl, " PCIe Cap offset : 0x%02x\n",
920 ctrl_info(ctrl, " PCI resource [%d] : %pR\n",
923 ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap);
924 ctrl_info(ctrl, " Physical Slot Number : %d\n", PSN(ctrl));
925 ctrl_info(ctrl, " Attention Button : %3s\n",
926 ATTN_BUTTN(ctrl) ? "yes" : "no");
927 ctrl_info(ctrl, " Power Controller : %3s\n",
928 POWER_CTRL(ctrl) ? "yes" : "no");
929 ctrl_info(ctrl, " MRL Sensor : %3s\n",
930 MRL_SENS(ctrl) ? "yes" : "no");
931 ctrl_info(ctrl, " Attention Indicator : %3s\n",
932 ATTN_LED(ctrl) ? "yes" : "no");
933 ctrl_info(ctrl, " Power Indicator : %3s\n",
934 PWR_LED(ctrl) ? "yes" : "no");
935 ctrl_info(ctrl, " Hot-Plug Surprise : %3s\n",
936 HP_SUPR_RM(ctrl) ? "yes" : "no");
937 ctrl_info(ctrl, " EMI Present : %3s\n",
938 EMI(ctrl) ? "yes" : "no");
939 ctrl_info(ctrl, " Command Completed : %3s\n",
940 NO_CMD_CMPL(ctrl) ? "no" : "yes");
941 pciehp_readw(ctrl, PCI_EXP_SLTSTA, ®16);
942 ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16);
943 pciehp_readw(ctrl, PCI_EXP_SLTCTL, ®16);
944 ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16);
949 struct controller *ctrl;
953 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
954 if (!ctrl) {
958 ctrl->pcie = dev;
960 ctrl_err(ctrl, "Cannot find PCI Express capability\n");
963 if (pciehp_readl(ctrl, PCI_EXP_SLTCAP, &slot_cap)) {
964 ctrl_err(ctrl, "Cannot read SLOTCAP register\n");
968 ctrl->slot_cap = slot_cap;
969 mutex_init(&ctrl->ctrl_lock);
970 init_waitqueue_head(&ctrl->queue);
971 dbg_ctrl(ctrl);
978 if (NO_CMD_CMPL(ctrl) ||
979 !(POWER_CTRL(ctrl) | ATTN_LED(ctrl) | PWR_LED(ctrl) | EMI(ctrl)))
980 ctrl->no_cmd_complete = 1;
983 if (pciehp_readl(ctrl, PCI_EXP_LNKCAP, &link_cap)) {
984 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__);
988 ctrl_dbg(ctrl, "Link Active Reporting supported\n");
989 ctrl->link_active_reporting = 1;
993 if (pciehp_writew(ctrl, PCI_EXP_SLTSTA, 0x1f))
997 pcie_disable_notification(ctrl);
999 ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",
1003 if (pcie_init_slot(ctrl))
1006 return ctrl;
1009 kfree(ctrl);
1014 void pciehp_release_ctrl(struct controller *ctrl)
1016 pcie_shutdown_notification(ctrl);
1017 pcie_cleanup_slot(ctrl);
1018 kfree(ctrl);