Lines Matching defs:p_slot
99 struct slot *p_slot;
180 extern int shpchp_configure_device(struct slot *p_slot);
181 extern int shpchp_unconfigure_device(struct slot *p_slot);
253 static inline void amd_pogo_errata_save_misc_reg(struct slot *p_slot)
258 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp);
260 p_slot->ctrl->pcix_misc2_reg = pcix_misc2_temp;
268 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);
271 static inline void amd_pogo_errata_restore_misc_reg(struct slot *p_slot)
280 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, &pcix_bridge_errors_reg);
283 ctrl_dbg(p_slot->ctrl,
287 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, perr_set);
291 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, &pcix_mem_base_reg);
294 ctrl_dbg(p_slot->ctrl, "Memory_Base_Limit[ RSE ] (W1C)\n");
296 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, rse_set);
299 pci_read_config_dword( p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp );
301 if (p_slot->ctrl->pcix_misc2_reg & SERRFATALENABLE_MASK)
306 if (p_slot->ctrl->pcix_misc2_reg & SERRNONFATALENABLE_MASK)
311 if (p_slot->ctrl->pcix_misc2_reg & PERRFLOODENABLE_MASK)
316 if (p_slot->ctrl->pcix_misc2_reg & PERRFATALENABLE_MASK)
321 if (p_slot->ctrl->pcix_misc2_reg & PERRNONFATALENABLE_MASK)
325 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);