Cross Reference: /drivers/pci/hotplug/shpchp.h

Lines Matching refs:ctrl
64 #define ctrl_dbg(ctrl, format, arg...)					\
67 			dev_printk(KERN_DEBUG, &ctrl->pci_dev->dev,	\
70 #define ctrl_err(ctrl, format, arg...)					\
71 	dev_err(&ctrl->pci_dev->dev, format, ## arg)
72 #define ctrl_info(ctrl, format, arg...)					\
73 	dev_info(&ctrl->pci_dev->dev, format, ## arg)
74 #define ctrl_warn(ctrl, format, arg...)					\
75 	dev_warn(&ctrl->pci_dev->dev, format, ## arg)
88 	struct controller *ctrl;
172 extern int __must_check shpchp_create_ctrl_files(struct controller *ctrl);
173 extern void shpchp_remove_ctrl_files(struct controller *ctrl);
176 extern u8 shpchp_handle_attention_button(u8 hp_slot, struct controller *ctrl);
177 extern u8 shpchp_handle_switch_change(u8 hp_slot, struct controller *ctrl);
178 extern u8 shpchp_handle_presence_change(u8 hp_slot, struct controller *ctrl);
179 extern u8 shpchp_handle_power_fault(u8 hp_slot, struct controller *ctrl);
182 extern void cleanup_slots(struct controller *ctrl);
184 extern int shpc_init( struct controller *ctrl, struct pci_dev *pdev);
240 static inline struct slot *shpchp_find_slot(struct controller *ctrl, u8 device)
244 	list_for_each_entry(slot, &ctrl->slot_list, slot_list) {
249 	ctrl_err(ctrl, "Slot (device=0x%02x) not found\n", device);
258 	pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp);
260 	p_slot->ctrl->pcix_misc2_reg = pcix_misc2_temp;
268 	pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);
280 	pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, &pcix_bridge_errors_reg);
283 		ctrl_dbg(p_slot->ctrl,
287 		pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, perr_set);
291 	pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, &pcix_mem_base_reg);
294 		ctrl_dbg(p_slot->ctrl, "Memory_Base_Limit[ RSE ] (W1C)\n");
296 		pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, rse_set);
299 	pci_read_config_dword( p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp );
301 	if (p_slot->ctrl->pcix_misc2_reg & SERRFATALENABLE_MASK)
306 	if (p_slot->ctrl->pcix_misc2_reg & SERRNONFATALENABLE_MASK)
311 	if (p_slot->ctrl->pcix_misc2_reg & PERRFLOODENABLE_MASK)
316 	if (p_slot->ctrl->pcix_misc2_reg & PERRFATALENABLE_MASK)
321 	if (p_slot->ctrl->pcix_misc2_reg & PERRNONFATALENABLE_MASK)
325 	pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);
345 	void (*release_ctlr)(struct controller *ctrl);
346 	int (*check_cmd_status)(struct controller *ctrl);