Lines Matching refs:ctrl
183 static void start_int_poll_timer(struct controller *ctrl, int sec);
184 static int hpc_check_cmd_status(struct controller *ctrl);
186 static inline u8 shpc_readb(struct controller *ctrl, int reg)
188 return readb(ctrl->creg + reg);
191 static inline void shpc_writeb(struct controller *ctrl, int reg, u8 val)
193 writeb(val, ctrl->creg + reg);
196 static inline u16 shpc_readw(struct controller *ctrl, int reg)
198 return readw(ctrl->creg + reg);
201 static inline void shpc_writew(struct controller *ctrl, int reg, u16 val)
203 writew(val, ctrl->creg + reg);
206 static inline u32 shpc_readl(struct controller *ctrl, int reg)
208 return readl(ctrl->creg + reg);
211 static inline void shpc_writel(struct controller *ctrl, int reg, u32 val)
213 writel(val, ctrl->creg + reg);
216 static inline int shpc_indirect_read(struct controller *ctrl, int index,
220 u32 cap_offset = ctrl->cap_offset;
221 struct pci_dev *pdev = ctrl->pci_dev;
234 struct controller *ctrl = (struct controller *)data;
237 shpc_isr(0, ctrl);
239 init_timer(&ctrl->poll_timer);
243 start_int_poll_timer(ctrl, shpchp_poll_time);
249 static void start_int_poll_timer(struct controller *ctrl, int sec)
255 ctrl->poll_timer.function = &int_poll_timeout;
256 ctrl->poll_timer.data = (unsigned long)ctrl;
257 ctrl->poll_timer.expires = jiffies + sec * HZ;
258 add_timer(&ctrl->poll_timer);
261 static inline int is_ctrl_busy(struct controller *ctrl)
263 u16 cmd_status = shpc_readw(ctrl, CMD_STATUS);
271 static inline int shpc_poll_ctrl_busy(struct controller *ctrl)
275 if (!is_ctrl_busy(ctrl))
281 if (!is_ctrl_busy(ctrl))
288 static inline int shpc_wait_cmd(struct controller *ctrl)
295 rc = shpc_poll_ctrl_busy(ctrl);
297 rc = wait_event_interruptible_timeout(ctrl->queue,
298 !is_ctrl_busy(ctrl), timeout);
299 if (!rc && is_ctrl_busy(ctrl)) {
301 ctrl_err(ctrl, "Command not completed in 1000 msec\n");
304 ctrl_info(ctrl, "Command was interrupted by a signal\n");
312 struct controller *ctrl = slot->ctrl;
317 mutex_lock(&slot->ctrl->cmd_lock);
319 if (!shpc_poll_ctrl_busy(ctrl)) {
321 ctrl_err(ctrl, "Controller is still busy after 1 sec\n");
328 ctrl_dbg(ctrl, "%s: t_slot %x cmd %x\n", __func__, t_slot, cmd);
333 shpc_writew(ctrl, CMD, temp_word);
338 retval = shpc_wait_cmd(slot->ctrl);
342 cmd_status = hpc_check_cmd_status(slot->ctrl);
344 ctrl_err(ctrl,
350 mutex_unlock(&slot->ctrl->cmd_lock);
354 static int hpc_check_cmd_status(struct controller *ctrl)
357 u16 cmd_status = shpc_readw(ctrl, CMD_STATUS) & 0x000F;
365 ctrl_err(ctrl, "Switch opened!\n");
369 ctrl_err(ctrl, "Invalid HPC command!\n");
373 ctrl_err(ctrl, "Invalid bus speed/mode!\n");
385 struct controller *ctrl = slot->ctrl;
386 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
409 struct controller *ctrl = slot->ctrl;
410 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
434 struct controller *ctrl = slot->ctrl;
435 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
444 struct controller *ctrl = slot->ctrl;
445 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
455 struct controller *ctrl = slot->ctrl;
457 *prog_int = shpc_readb(ctrl, PROG_INTERFACE);
465 struct controller *ctrl = slot->ctrl;
466 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
484 ctrl_dbg(ctrl, "%s: slot_reg = %x, pcix_cap = %x, m66_cap = %x\n",
510 ctrl_dbg(ctrl, "Adapter speed = %d\n", *value);
517 struct controller *ctrl = slot->ctrl;
518 u16 sec_bus_status = shpc_readw(ctrl, SEC_BUS_CONFIG);
519 u8 pi = shpc_readb(ctrl, PROG_INTERFACE);
527 ctrl_dbg(ctrl, "Mode 1 ECC cap = %d\n", *mode);
533 struct controller *ctrl = slot->ctrl;
534 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
577 static void hpc_release_ctlr(struct controller *ctrl)
585 for (i = 0; i < ctrl->num_slots; i++) {
586 slot_reg = shpc_readl(ctrl, SLOT_REG(i));
592 shpc_writel(ctrl, SLOT_REG(i), slot_reg);
595 cleanup_slots(ctrl);
600 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
604 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
607 del_timer(&ctrl->poll_timer);
609 free_irq(ctrl->pci_dev->irq, ctrl);
610 pci_disable_msi(ctrl->pci_dev);
613 iounmap(ctrl->creg);
614 release_mem_region(ctrl->mmio_base, ctrl->mmio_size);
623 ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__);
636 ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__);
649 ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__);
654 static int shpc_get_cur_bus_speed(struct controller *ctrl)
657 struct pci_bus *bus = ctrl->pci_dev->subordinate;
659 u16 sec_bus_reg = shpc_readw(ctrl, SEC_BUS_CONFIG);
660 u8 pi = shpc_readb(ctrl, PROG_INTERFACE);
726 struct controller *ctrl = slot->ctrl;
729 pi = shpc_readb(ctrl, PROG_INTERFACE);
782 ctrl_err(ctrl, "%s: Write command failed!\n", __func__);
784 shpc_get_cur_bus_speed(ctrl);
791 struct controller *ctrl = (struct controller *)dev_id;
796 intr_loc = shpc_readl(ctrl, INTR_LOC);
800 ctrl_dbg(ctrl, "%s: intr_loc = %x\n", __func__, intr_loc);
807 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
810 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
812 intr_loc2 = shpc_readl(ctrl, INTR_LOC);
813 ctrl_dbg(ctrl, "%s: intr_loc2 = %x\n", __func__, intr_loc2);
822 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
824 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
826 wake_up_interruptible(&ctrl->queue);
832 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
837 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
838 ctrl_dbg(ctrl, "Slot %x with intr, slot register = %x\n",
842 shpchp_handle_switch_change(hp_slot, ctrl);
845 shpchp_handle_attention_button(hp_slot, ctrl);
848 shpchp_handle_presence_change(hp_slot, ctrl);
851 shpchp_handle_power_fault(hp_slot, ctrl);
855 shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
860 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
862 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
868 static int shpc_get_max_bus_speed(struct controller *ctrl)
871 struct pci_bus *bus = ctrl->pci_dev->subordinate;
873 u8 pi = shpc_readb(ctrl, PROG_INTERFACE);
874 u32 slot_avail1 = shpc_readl(ctrl, SLOT_AVAIL1);
875 u32 slot_avail2 = shpc_readl(ctrl, SLOT_AVAIL2);
908 ctrl_dbg(ctrl, "Max bus speed = %d\n", bus_speed);
936 int shpc_init(struct controller *ctrl, struct pci_dev *pdev)
944 ctrl->pci_dev = pdev; /* pci_dev of the P2P bridge */
945 ctrl_dbg(ctrl, "Hotplug Controller:\n");
950 ctrl->mmio_base = pci_resource_start(pdev, 0);
951 ctrl->mmio_size = pci_resource_len(pdev, 0);
953 ctrl->cap_offset = pci_find_capability(pdev, PCI_CAP_ID_SHPC);
954 if (!ctrl->cap_offset) {
955 ctrl_err(ctrl, "Cannot find PCI capability\n");
958 ctrl_dbg(ctrl, " cap_offset = %x\n", ctrl->cap_offset);
960 rc = shpc_indirect_read(ctrl, 0, &shpc_base_offset);
962 ctrl_err(ctrl, "Cannot read base_offset\n");
966 rc = shpc_indirect_read(ctrl, 3, &tempdword);
968 ctrl_err(ctrl, "Cannot read slot config\n");
972 ctrl_dbg(ctrl, " num_slots (indirect) %x\n", num_slots);
975 rc = shpc_indirect_read(ctrl, i, &tempdword);
977 ctrl_err(ctrl,
981 ctrl_dbg(ctrl, " offset %d: value %x\n", i, tempdword);
984 ctrl->mmio_base =
986 ctrl->mmio_size = 0x24 + 0x4 * num_slots;
989 ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",
995 ctrl_err(ctrl, "pci_enable_device failed\n");
999 if (!request_mem_region(ctrl->mmio_base, ctrl->mmio_size, MY_NAME)) {
1000 ctrl_err(ctrl, "Cannot reserve MMIO region\n");
1005 ctrl->creg = ioremap(ctrl->mmio_base, ctrl->mmio_size);
1006 if (!ctrl->creg) {
1007 ctrl_err(ctrl, "Cannot remap MMIO region %lx @ %lx\n",
1008 ctrl->mmio_size, ctrl->mmio_base);
1009 release_mem_region(ctrl->mmio_base, ctrl->mmio_size);
1013 ctrl_dbg(ctrl, "ctrl->creg %p\n", ctrl->creg);
1015 mutex_init(&ctrl->crit_sect);
1016 mutex_init(&ctrl->cmd_lock);
1019 init_waitqueue_head(&ctrl->queue);
1021 ctrl->hpc_ops = &shpchp_hpc_ops;
1024 slot_config = shpc_readl(ctrl, SLOT_CONFIG);
1025 ctrl->slot_device_offset = (slot_config & FIRST_DEV_NUM) >> 8;
1026 ctrl->num_slots = slot_config & SLOT_NUM;
1027 ctrl->first_slot = (slot_config & PSN) >> 16;
1028 ctrl->slot_num_inc = ((slot_config & UPDOWN) >> 29) ? 1 : -1;
1031 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1032 ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword);
1036 shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);
1037 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1038 ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword);
1043 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
1044 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
1045 ctrl_dbg(ctrl, "Default Logical Slot Register %d value %x\n",
1052 shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
1057 init_timer(&ctrl->poll_timer);
1058 start_int_poll_timer(ctrl, 10);
1063 ctrl_info(ctrl,
1065 ctrl_info(ctrl,
1069 rc = request_irq(ctrl->pci_dev->irq, shpc_isr, IRQF_SHARED,
1070 MY_NAME, (void *)ctrl);
1071 ctrl_dbg(ctrl, "request_irq %d (returns %d)\n",
1072 ctrl->pci_dev->irq, rc);
1074 ctrl_err(ctrl, "Can't get irq %d for the hotplug "
1075 "controller\n", ctrl->pci_dev->irq);
1079 ctrl_dbg(ctrl, "HPC at %s irq=%x\n", pci_name(pdev), pdev->irq);
1081 shpc_get_max_bus_speed(ctrl);
1082 shpc_get_cur_bus_speed(ctrl);
1087 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
1088 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
1089 ctrl_dbg(ctrl, "Default Logical Slot Register %d value %x\n",
1094 shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
1098 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1101 shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);
1102 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1103 ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword);
1110 iounmap(ctrl->creg);