Lines Matching refs:cap
165 u8 pos, int cap, int *ttl)
178 if (id == cap)
186 u8 pos, int cap)
190 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
193 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
196 pos + PCI_CAP_LIST_NEXT, cap);
225 * @cap: capability code
230 * support it. Possible values for @cap:
241 int pci_find_capability(struct pci_dev *dev, int cap)
247 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
256 * @cap: capability code
265 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
274 pos = __pci_find_next_cap(bus, devfn, pos, cap);
282 * @cap: capability code
286 * not support it. Possible values for @cap:
293 int pci_find_ext_capability(struct pci_dev *dev, int cap)
309 * If we have no capabilities, this is indicated by cap ID,
310 * cap version and next pointer all being 0.
316 if (PCI_EXT_CAP_ID(header) == cap)
335 * @cap: capability code
345 int cap)
360 if (PCI_EXT_CAP_ID(header) == cap)
377 u8 cap, mask;
387 rc = pci_read_config_byte(dev, pos + 3, &cap);
391 if ((cap & mask) == ht_cap)
832 struct pci_dev *pci_dev, char cap)
838 if (tmp->cap.cap_nr == cap)
848 u16 *cap;
860 cap = (u16 *)&save_state->cap.data[0];
865 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]);
867 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
869 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
871 pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
873 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &cap[i++]);
875 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL2, &cap[i++]);
877 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL2, &cap[i++]);
886 u16 *cap;
893 cap = (u16 *)&save_state->cap.data[0];
898 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
900 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
902 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
904 pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
906 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, cap[i++]);
908 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL2, cap[i++]);
910 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL2, cap[i++]);
930 (u16 *)save_state->cap.data);
939 u16 *cap;
945 cap = (u16 *)&save_state->cap.data[0];
947 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
1041 struct pci_cap_saved_data cap[0];
1055 struct pci_cap_saved_data *cap;
1065 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1074 cap = state->cap;
1076 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1077 memcpy(cap, &tmp->cap, len);
1078 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1093 struct pci_cap_saved_data *cap;
1103 cap = state->cap;
1104 while (cap->size) {
1107 tmp = pci_find_saved_cap(dev, cap->cap_nr);
1108 if (!tmp || tmp->cap.size != cap->size)
1111 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1112 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1113 sizeof(struct pci_cap_saved_data) + cap->size);
1851 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
1924 * @cap: the capability to allocate the buffer for
1928 struct pci_dev *dev, char cap, unsigned int size)
1933 pos = pci_find_capability(dev, cap);
1941 save_state->cap.cap_nr = cap;
1942 save_state->cap.size = size;
1984 u32 cap;
2008 pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap);
2009 if (!(cap & PCI_EXP_DEVCAP2_ARI))
2094 u32 cap;
2105 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP2, &cap);
2106 if (!(cap & PCI_EXP_OBFF_MASK))
2117 if (cap & PCI_EXP_OBFF_WAKE)
2174 u32 cap;
2183 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP2, &cap);
2185 return cap & PCI_EXP_DEVCAP2_LTR;
2330 u16 cap;
2343 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
2347 ctrl |= (cap & PCI_ACS_SV);
2350 ctrl |= (cap & PCI_ACS_RR);
2353 ctrl |= (cap & PCI_ACS_CR);
2356 ctrl |= (cap & PCI_ACS_UF);
3020 u32 cap;
3027 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP, &cap);
3028 if (!(cap & PCI_EXP_DEVCAP_FLR))
3061 u8 cap;
3068 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
3069 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
3318 int cap;
3321 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3322 if (!cap)
3325 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
3341 int cap;
3344 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3345 if (!cap)
3348 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
3366 int cap;
3375 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3376 if (!cap)
3379 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
3385 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
3396 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
3412 int ret, cap;
3415 cap = pci_pcie_cap(dev);
3416 if (!cap)
3419 ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
3437 int cap, err = -EINVAL;
3443 cap = pci_pcie_cap(dev);
3444 if (!cap)
3447 err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
3470 err = pci_write_config_word(dev, cap + PCI_EXP_DEVCTL, ctl);
3487 int ret, cap;
3490 cap = pci_pcie_cap(dev);
3491 if (!cap)
3494 ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
3511 int cap, err = -EINVAL;
3522 cap = pci_pcie_cap(dev);
3523 if (!cap)
3526 err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
3533 err = pci_write_config_word(dev, cap + PCI_EXP_DEVCTL, ctl);