Cross Reference: /drivers/scsi/bfa/bfa_ioc

Lines Matching defs:rb
110 	void __iomem *rb;
113 	rb = bfa_ioc_bar0(ioc);
115 	ioc->ioc_regs.hfn_mbox = rb + iocreg_fnreg[pcifn].hfn_mbox;
116 	ioc->ioc_regs.lpu_mbox = rb + iocreg_fnreg[pcifn].lpu_mbox;
117 	ioc->ioc_regs.host_page_num_fn = rb + iocreg_fnreg[pcifn].hfn_pgn;
120 		ioc->ioc_regs.heartbeat = rb + BFA_IOC0_HBEAT_REG;
121 		ioc->ioc_regs.ioc_fwstate = rb + BFA_IOC0_STATE_REG;
122 		ioc->ioc_regs.alt_ioc_fwstate = rb + BFA_IOC1_STATE_REG;
124 		ioc->ioc_regs.heartbeat = (rb + BFA_IOC1_HBEAT_REG);
125 		ioc->ioc_regs.ioc_fwstate = (rb + BFA_IOC1_STATE_REG);
126 		ioc->ioc_regs.alt_ioc_fwstate = (rb + BFA_IOC0_STATE_REG);
132 	ioc->ioc_regs.hfn_mbox_cmd = rb + iocreg_mbcmd[pcifn].hfn;
133 	ioc->ioc_regs.lpu_mbox_cmd = rb + iocreg_mbcmd[pcifn].lpu;
138 	ioc->ioc_regs.pss_ctl_reg = (rb + PSS_CTL_REG);
139 	ioc->ioc_regs.pss_err_status_reg = (rb + PSS_ERR_STATUS_REG);
140 	ioc->ioc_regs.app_pll_fast_ctl_reg = (rb + APP_PLL_LCLK_CTL_REG);
141 	ioc->ioc_regs.app_pll_slow_ctl_reg = (rb + APP_PLL_SCLK_CTL_REG);
146 	ioc->ioc_regs.ioc_sem_reg = (rb + HOST_SEM0_REG);
147 	ioc->ioc_regs.ioc_init_sem_reg = (rb + HOST_SEM2_REG);
152 	ioc->ioc_regs.smem_page_start = (rb + PSS_SMEM_PAGE_START);
158 	ioc->ioc_regs.err_set = (rb + ERR_SET_REG);
273 bfa_ioc_cb_pll_init(void __iomem *rb, enum bfi_asic_mode fcmode)
285 	writel(BFI_IOC_UNINIT, (rb + BFA_IOC0_STATE_REG));
286 	writel(BFI_IOC_UNINIT, (rb + BFA_IOC1_STATE_REG));
287 	writel(0xffffffffU, (rb + HOSTFN0_INT_MSK));
288 	writel(0xffffffffU, (rb + HOSTFN1_INT_MSK));
289 	writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS));
290 	writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS));
291 	writel(0xffffffffU, (rb + HOSTFN0_INT_MSK));
292 	writel(0xffffffffU, (rb + HOSTFN1_INT_MSK));
293 	writel(__APP_PLL_SCLK_LOGIC_SOFT_RESET, rb + APP_PLL_SCLK_CTL_REG);
295 			rb + APP_PLL_SCLK_CTL_REG);
296 	writel(__APP_PLL_LCLK_LOGIC_SOFT_RESET, rb + APP_PLL_LCLK_CTL_REG);
298 			rb + APP_PLL_LCLK_CTL_REG);
300 	writel(__APP_PLL_SCLK_LOGIC_SOFT_RESET, rb + APP_PLL_SCLK_CTL_REG);
301 	writel(__APP_PLL_LCLK_LOGIC_SOFT_RESET, rb + APP_PLL_LCLK_CTL_REG);
303 			rb + APP_PLL_SCLK_CTL_REG);
305 			rb + APP_PLL_LCLK_CTL_REG);
307 	writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS));
308 	writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS));
309 	writel(pll_sclk, (rb + APP_PLL_SCLK_CTL_REG));
310 	writel(pll_fclk, (rb + APP_PLL_LCLK_CTL_REG));