Lines Matching refs:mvi
30 static void mvs_64xx_detect_porttype(struct mvs_info *mvi, int i)
32 void __iomem *regs = mvi->regs;
34 struct mvs_phy *phy = &mvi->phy[i];
44 static void __devinit mvs_64xx_enable_xmt(struct mvs_info *mvi, int phy_id)
46 void __iomem *regs = mvi->regs;
50 if (mvi->chip->n_phy <= MVS_SOC_PORTS)
57 static void __devinit mvs_64xx_phy_hacks(struct mvs_info *mvi)
59 void __iomem *regs = mvi->regs;
62 mvs_phy_hacks(mvi);
64 if (!(mvi->flags & MVF_FLAG_SOC)) {
66 mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE8);
67 mvs_write_port_vsr_data(mvi, i, 0x2F0);
72 for (i = 0; i < mvi->chip->n_phy; i++) {
73 mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE7);
74 mvs_write_port_vsr_data(mvi, i, 0x90000000);
75 mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE9);
76 mvs_write_port_vsr_data(mvi, i, 0x50f2);
77 mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE11);
78 mvs_write_port_vsr_data(mvi, i, 0x0e);
83 static void mvs_64xx_stp_reset(struct mvs_info *mvi, u32 phy_id)
85 void __iomem *regs = mvi->regs;
88 if (!(mvi->flags & MVF_FLAG_SOC)) {
90 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL, ®);
92 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL2, ®);
103 if (!(mvi->flags & MVF_FLAG_SOC)) {
105 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, tmp);
107 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, reg);
109 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, tmp);
111 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, reg);
120 static void mvs_64xx_phy_reset(struct mvs_info *mvi, u32 phy_id, int hard)
123 tmp = mvs_read_port_irq_stat(mvi, phy_id);
125 mvs_write_port_irq_stat(mvi, phy_id, tmp);
126 tmp = mvs_read_phy_ctl(mvi, phy_id);
131 mvs_write_phy_ctl(mvi, phy_id, tmp);
134 tmp = mvs_read_phy_ctl(mvi, phy_id);
139 void mvs_64xx_clear_srs_irq(struct mvs_info *mvi, u8 reg_set, u8 clear_all)
141 void __iomem *regs = mvi->regs;
159 static int __devinit mvs_64xx_chip_reset(struct mvs_info *mvi)
161 void __iomem *regs = mvi->regs;
171 if (mvi->flags & MVF_PHY_PWR_FIX) {
172 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL, &tmp);
175 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, tmp);
177 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL2, &tmp);
180 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, tmp);
203 dev_printk(KERN_ERR, mvi->dev, "HBA reset failed\n");
209 static void mvs_64xx_phy_disable(struct mvs_info *mvi, u32 phy_id)
211 void __iomem *regs = mvi->regs;
213 if (!(mvi->flags & MVF_FLAG_SOC)) {
221 pci_read_config_dword(mvi->pdev, offs, &tmp);
223 pci_write_config_dword(mvi->pdev, offs, tmp);
231 static void mvs_64xx_phy_enable(struct mvs_info *mvi, u32 phy_id)
233 void __iomem *regs = mvi->regs;
235 if (!(mvi->flags & MVF_FLAG_SOC)) {
243 pci_read_config_dword(mvi->pdev, offs, &tmp);
245 pci_write_config_dword(mvi->pdev, offs, tmp);
253 static int __devinit mvs_64xx_init(struct mvs_info *mvi)
255 void __iomem *regs = mvi->regs;
259 if (mvi->pdev && mvi->pdev->revision == 0)
260 mvi->flags |= MVF_PHY_PWR_FIX;
261 if (!(mvi->flags & MVF_FLAG_SOC)) {
262 mvs_show_pcie_usage(mvi);
263 tmp = mvs_64xx_chip_reset(mvi);
281 if (!(mvi->flags & MVF_FLAG_SOC)) {
283 pci_read_config_dword(mvi->pdev, PCR_DEV_CTRL, &tmp);
286 pci_write_config_dword(mvi->pdev, PCR_DEV_CTRL, tmp);
288 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL, &tmp);
291 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, tmp);
293 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL2, &tmp);
296 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, tmp);
313 mvs_64xx_phy_hacks(mvi);
315 tmp = mvs_cr32(mvi, CMD_PHY_MODE_21);
318 mvs_cw32(mvi, CMD_PHY_MODE_21, tmp);
323 mw32(MVS_CMD_LIST_LO, mvi->slot_dma);
324 mw32(MVS_CMD_LIST_HI, (mvi->slot_dma >> 16) >> 16);
326 mw32(MVS_RX_FIS_LO, mvi->rx_fis_dma);
327 mw32(MVS_RX_FIS_HI, (mvi->rx_fis_dma >> 16) >> 16);
330 mw32(MVS_TX_LO, mvi->tx_dma);
331 mw32(MVS_TX_HI, (mvi->tx_dma >> 16) >> 16);
334 mw32(MVS_RX_LO, mvi->rx_dma);
335 mw32(MVS_RX_HI, (mvi->rx_dma >> 16) >> 16);
337 for (i = 0; i < mvi->chip->n_phy; i++) {
340 mvs_set_sas_addr(mvi, i, PHYR_ADDR_LO, PHYR_ADDR_HI,
341 cpu_to_be64(mvi->phy[i].dev_sas_addr));
343 mvs_64xx_enable_xmt(mvi, i);
345 mvs_64xx_phy_reset(mvi, i, MVS_HARD_RESET);
347 mvs_64xx_detect_porttype(mvi, i);
349 if (mvi->flags & MVF_FLAG_SOC) {
360 for (i = 0; i < mvi->chip->n_phy; i++) {
362 tmp = mvs_read_port_irq_stat(mvi, i);
364 mvs_write_port_irq_stat(mvi, i, tmp);
370 mvs_write_port_irq_mask(mvi, i, tmp);
373 mvs_update_phyinfo(mvi, i, 1);
422 static int mvs_64xx_ioremap(struct mvs_info *mvi)
424 if (!mvs_ioremap(mvi, 4, 2))
429 static void mvs_64xx_iounmap(struct mvs_info *mvi)
431 mvs_iounmap(mvi->regs);
432 mvs_iounmap(mvi->regs_ex);
435 static void mvs_64xx_interrupt_enable(struct mvs_info *mvi)
437 void __iomem *regs = mvi->regs;
444 static void mvs_64xx_interrupt_disable(struct mvs_info *mvi)
446 void __iomem *regs = mvi->regs;
453 static u32 mvs_64xx_isr_status(struct mvs_info *mvi, int irq)
455 void __iomem *regs = mvi->regs;
458 if (!(mvi->flags & MVF_FLAG_SOC)) {
468 static irqreturn_t mvs_64xx_isr(struct mvs_info *mvi, int irq, u32 stat)
470 void __iomem *regs = mvi->regs;
475 spin_lock(&mvi->lock);
476 mvs_int_full(mvi);
477 spin_unlock(&mvi->lock);
482 static void mvs_64xx_command_active(struct mvs_info *mvi, u32 slot_idx)
485 mvs_cw32(mvi, 0x40 + (slot_idx >> 3), 1 << (slot_idx % 32));
486 mvs_cw32(mvi, 0x00 + (slot_idx >> 3), 1 << (slot_idx % 32));
488 tmp = mvs_cr32(mvi, 0x00 + (slot_idx >> 3));
491 tmp = mvs_cr32(mvi, 0x40 + (slot_idx >> 3));
495 static void mvs_64xx_issue_stop(struct mvs_info *mvi, enum mvs_port_type type,
498 void __iomem *regs = mvi->regs;
510 static void mvs_64xx_free_reg_set(struct mvs_info *mvi, u8 *tfs)
512 void __iomem *regs = mvi->regs;
535 static u8 mvs_64xx_assign_reg_set(struct mvs_info *mvi, u8 *tfs)
539 void __iomem *regs = mvi->regs;
546 for (i = 0; i < mvi->chip->srs_sz; i++) {
578 static int mvs_64xx_oob_done(struct mvs_info *mvi, int i)
581 mvs_write_port_cfg_addr(mvi, i,
583 phy_st = mvs_read_port_cfg_data(mvi, i);
589 static void mvs_64xx_fix_phy_info(struct mvs_info *mvi, int i,
593 struct mvs_phy *phy = &mvi->phy[i];
607 mvs_write_port_cfg_addr(mvi, i, PHYR_IDENTIFY);
608 phy->dev_info = mvs_read_port_cfg_data(mvi, i);
610 mvs_write_port_cfg_addr(mvi, i, PHYR_ATT_DEV_INFO);
611 phy->att_dev_info = mvs_read_port_cfg_data(mvi, i);
613 mvs_write_port_cfg_addr(mvi, i, PHYR_ATT_ADDR_HI);
615 (u64) mvs_read_port_cfg_data(mvi, i) << 32;
616 mvs_write_port_cfg_addr(mvi, i, PHYR_ATT_ADDR_LO);
617 phy->att_dev_sas_addr |= mvs_read_port_cfg_data(mvi, i);
621 static void mvs_64xx_phy_work_around(struct mvs_info *mvi, int i)
624 struct mvs_phy *phy = &mvi->phy[i];
625 mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE6);
626 tmp = mvs_read_port_vsr_data(mvi, i);
633 mvs_write_port_vsr_data(mvi, i, tmp);
636 void mvs_64xx_phy_set_link_rate(struct mvs_info *mvi, u32 phy_id,
642 tmp = mvs_read_phy_ctl(mvi, phy_id);
654 mvs_write_phy_ctl(mvi, phy_id, tmp);
655 mvs_64xx_phy_reset(mvi, phy_id, MVS_HARD_RESET);
658 static void mvs_64xx_clear_active_cmds(struct mvs_info *mvi)
661 void __iomem *regs = mvi->regs;
671 u32 mvs_64xx_spi_read_data(struct mvs_info *mvi)
673 void __iomem *regs = mvi->regs_ex;
677 void mvs_64xx_spi_write_data(struct mvs_info *mvi, u32 data)
679 void __iomem *regs = mvi->regs_ex;
684 int mvs_64xx_spi_buildcmd(struct mvs_info *mvi,
708 int mvs_64xx_spi_issuecmd(struct mvs_info *mvi, u32 cmd)
710 void __iomem *regs = mvi->regs_ex;
723 int mvs_64xx_spi_waitdataready(struct mvs_info *mvi, u32 timeout)
725 void __iomem *regs = mvi->regs_ex;
738 void mvs_64xx_fix_dma(struct mvs_info *mvi, u32 phy_mask,
743 dma_addr_t buf_dma = mvi->bulk_buffer_dma;
753 static void mvs_64xx_tune_interrupt(struct mvs_info *mvi, u32 time)
755 void __iomem *regs = mvi->regs;