Lines Matching refs:mvi
28 static int mvs_find_tag(struct mvs_info *mvi, struct sas_task *task, u32 *tag)
39 void mvs_tag_clear(struct mvs_info *mvi, u32 tag)
41 void *bitmap = mvi->tags;
45 void mvs_tag_free(struct mvs_info *mvi, u32 tag)
47 mvs_tag_clear(mvi, tag);
50 void mvs_tag_set(struct mvs_info *mvi, unsigned int tag)
52 void *bitmap = mvi->tags;
56 inline int mvs_tag_alloc(struct mvs_info *mvi, u32 *tag_out)
59 void *bitmap = mvi->tags;
61 index = find_first_zero_bit(bitmap, mvi->tags_num);
63 if (tag >= mvi->tags_num)
65 mvs_tag_set(mvi, tag);
70 void mvs_tag_init(struct mvs_info *mvi)
73 for (i = 0; i < mvi->tags_num; ++i)
74 mvs_tag_clear(mvi, i);
81 struct mvs_info *mvi = NULL;
99 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[hi];
101 return mvi;
109 struct mvs_info *mvi = mvi_dev->mvi_info;
123 phyno[n] = (j >= mvi->chip->n_phy) ?
124 (j - mvi->chip->n_phy) : j;
135 struct mvs_device *mvs_find_dev_by_reg_set(struct mvs_info *mvi,
140 if (mvi->devices[dev_no].taskfileset == MVS_ID_NOT_MAPPED)
143 if (mvi->devices[dev_no].taskfileset == reg_set)
144 return &mvi->devices[dev_no];
149 static inline void mvs_free_reg_set(struct mvs_info *mvi,
158 MVS_CHIP_DISP->free_reg_set(mvi, &dev->taskfileset);
161 static inline u8 mvs_assign_reg_set(struct mvs_info *mvi,
166 return MVS_CHIP_DISP->assign_reg_set(mvi, &dev->taskfileset);
169 void mvs_phys_reset(struct mvs_info *mvi, u32 phy_mask, int hard)
175 MVS_CHIP_DISP->phy_reset(mvi, no, hard);
185 struct mvs_info *mvi = NULL;
193 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[hi];
197 MVS_CHIP_DISP->phy_set_link_rate(mvi, phy_id, funcdata);
201 tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, phy_id);
204 MVS_CHIP_DISP->phy_reset(mvi, phy_id, MVS_HARD_RESET);
208 MVS_CHIP_DISP->phy_enable(mvi, phy_id);
209 MVS_CHIP_DISP->phy_reset(mvi, phy_id, MVS_SOFT_RESET);
213 MVS_CHIP_DISP->phy_disable(mvi, phy_id);
223 void __devinit mvs_set_sas_addr(struct mvs_info *mvi, int port_id,
229 MVS_CHIP_DISP->write_port_cfg_addr(mvi, port_id, off_lo);
230 MVS_CHIP_DISP->write_port_cfg_data(mvi, port_id, lo);
231 MVS_CHIP_DISP->write_port_cfg_addr(mvi, port_id, off_hi);
232 MVS_CHIP_DISP->write_port_cfg_data(mvi, port_id, hi);
235 static void mvs_bytes_dmaed(struct mvs_info *mvi, int i)
237 struct mvs_phy *phy = &mvi->phy[i];
248 sas_ha = mvi->sas;
271 MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_PHY_STAT);
272 MVS_CHIP_DISP->write_port_cfg_data(mvi, i, 0x00);
277 mv_dprintk("phy %d byte dmaded.\n", i + mvi->id * mvi->chip->n_phy);
281 mvi->sas->notify_port_event(sas_phy,
289 struct mvs_info *mvi;
296 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[j];
297 for (i = 0; i < mvi->chip->n_phy; ++i)
298 mvs_bytes_dmaed(mvi, i);
315 static int mvs_task_prep_smp(struct mvs_info *mvi,
329 struct mvs_slot_info *slot = &mvi->slot_info[tag];
336 elem = dma_map_sg(mvi->dev, sg_req, 1, PCI_DMA_TODEVICE);
342 elem = dma_map_sg(mvi->dev, sg_resp, 1, PCI_DMA_FROMDEVICE);
386 if (mvi->flags & MVF_FLAG_SOC)
392 slot->tx = mvi->tx_prod;
393 mvi->tx[mvi->tx_prod] = cpu_to_le32((TXQ_CMD_SMP << TXQ_CMD_SHIFT) |
415 dma_unmap_sg(mvi->dev, &tei->task->smp_task.smp_resp, 1,
418 dma_unmap_sg(mvi->dev, &tei->task->smp_task.smp_req, 1,
438 static int mvs_task_prep_ata(struct mvs_info *mvi,
456 if (mvs_assign_reg_set(mvi, mvi_dev) == MVS_ID_NOT_MAPPED) {
461 slot = &mvi->slot_info[tag];
462 slot->tx = mvi->tx_prod;
467 mvi->tx[mvi->tx_prod] = cpu_to_le32(del_q);
528 if (mvi->flags & MVF_FLAG_SOC)
558 MVS_CHIP_DISP->dma_fix(mvi, sas_port->phy_mask,
564 static int mvs_task_prep_ssp(struct mvs_info *mvi,
585 slot = &mvi->slot_info[tag];
590 slot->tx = mvi->tx_prod;
591 mvi->tx[mvi->tx_prod] = cpu_to_le32(TXQ_MODE_I | tag |
643 if (mvi->flags & MVF_FLAG_SOC)
704 static int mvs_task_prep(struct sas_task *task, struct mvs_info *mvi, int is_tmf,
763 n_elem = dma_map_sg(mvi->dev,
776 rc = mvs_tag_alloc(mvi, &tag);
780 slot = &mvi->slot_info[tag];
786 slot->buf = pci_pool_alloc(mvi->dma_pool, GFP_ATOMIC, &slot->buf_dma);
792 tei.hdr = &mvi->slot[tag];
797 rc = mvs_task_prep_smp(mvi, &tei);
800 rc = mvs_task_prep_ssp(mvi, &tei, is_tmf, tmf);
805 rc = mvs_task_prep_ata(mvi, &tei);
808 dev_printk(KERN_ERR, mvi->dev,
829 mvi->tx_prod = (mvi->tx_prod + 1) & (MVS_CHIP_SLOT_SZ - 1);
834 pci_pool_free(mvi->dma_pool, slot->buf, slot->buf_dma);
836 mvs_tag_free(mvi, tag);
839 dev_printk(KERN_ERR, mvi->dev, "mvsas prep failed[%d]!\n", rc);
842 dma_unmap_sg(mvi->dev, task->scatter, n_elem,
889 struct mvs_info *mvi = NULL;
894 mvi = ((struct mvs_device *)task->dev->lldd_dev)->mvi_info;
896 spin_lock_irqsave(&mvi->lock, flags);
897 rc = mvs_task_prep(task, mvi, is_tmf, tmf, &pass);
899 dev_printk(KERN_ERR, mvi->dev, "mvsas exec failed[%d]!\n", rc);
902 MVS_CHIP_DISP->start_delivery(mvi, (mvi->tx_prod - 1) &
904 spin_unlock_irqrestore(&mvi->lock, flags);
915 struct mvs_info *mvi = NULL;
941 mvi = ((struct mvs_device *)t->dev->lldd_dev)->mvi_info;
943 spin_lock_irqsave(&mvi->lock, flags);
944 rc = mvs_task_prep(t, mvi, is_tmf, tmf, &pass[mvi->id]);
946 dev_printk(KERN_ERR, mvi->dev, "mvsas exec failed[%d]!\n", rc);
947 spin_unlock_irqrestore(&mvi->lock, flags);
951 MVS_CHIP_DISP->start_delivery(mpi->mvi[0],
952 (mpi->mvi[0]->tx_prod - 1) & (MVS_CHIP_SLOT_SZ - 1));
955 MVS_CHIP_DISP->start_delivery(mpi->mvi[1],
956 (mpi->mvi[1]->tx_prod - 1) & (MVS_CHIP_SLOT_SZ - 1));
979 static void mvs_slot_free(struct mvs_info *mvi, u32 rx_desc)
982 mvs_tag_clear(mvi, slot_idx);
985 static void mvs_slot_task_free(struct mvs_info *mvi, struct sas_task *task,
992 dma_unmap_sg(mvi->dev, task->scatter,
997 dma_unmap_sg(mvi->dev, &task->smp_task.smp_resp, 1,
999 dma_unmap_sg(mvi->dev, &task->smp_task.smp_req, 1,
1012 pci_pool_free(mvi->dma_pool, slot->buf, slot->buf_dma);
1020 mvs_slot_free(mvi, slot_idx);
1023 static void mvs_update_wideport(struct mvs_info *mvi, int phy_no)
1025 struct mvs_phy *phy = &mvi->phy[phy_no];
1031 MVS_CHIP_DISP->write_port_cfg_addr(mvi, no,
1033 MVS_CHIP_DISP->write_port_cfg_data(mvi, no,
1036 MVS_CHIP_DISP->write_port_cfg_addr(mvi, no,
1038 MVS_CHIP_DISP->write_port_cfg_data(mvi, no,
1044 static u32 mvs_is_phy_ready(struct mvs_info *mvi, int i)
1047 struct mvs_phy *phy = &mvi->phy[i];
1050 tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, i);
1062 mvs_update_wideport(mvi, i);
1072 static void *mvs_get_d2h_reg(struct mvs_info *mvi, int i, void *buf)
1079 MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG3);
1080 s[3] = cpu_to_le32(MVS_CHIP_DISP->read_port_cfg_data(mvi, i));
1082 MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG2);
1083 s[2] = cpu_to_le32(MVS_CHIP_DISP->read_port_cfg_data(mvi, i));
1085 MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG1);
1086 s[1] = cpu_to_le32(MVS_CHIP_DISP->read_port_cfg_data(mvi, i));
1088 MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG0);
1089 s[0] = cpu_to_le32(MVS_CHIP_DISP->read_port_cfg_data(mvi, i));
1109 void mvs_update_phyinfo(struct mvs_info *mvi, int i, int get_st)
1111 struct mvs_phy *phy = &mvi->phy[i];
1117 phy->irq_status = MVS_CHIP_DISP->read_port_irq_stat(mvi, i);
1118 phy->phy_status = mvs_is_phy_ready(mvi, i);
1123 struct asd_sas_phy *sas_phy = &mvi->phy[i].sas_phy;
1125 oob_done = MVS_CHIP_DISP->oob_done(mvi, i);
1127 MVS_CHIP_DISP->fix_phy_info(mvi, i, id);
1134 i + mvi->id * mvi->chip->n_phy;
1139 mvs_get_d2h_reg(mvi, i, id);
1142 dev_printk(KERN_DEBUG, mvi->dev,
1144 tmp = MVS_CHIP_DISP->read_port_irq_mask(mvi, i);
1145 MVS_CHIP_DISP->write_port_irq_mask(mvi, i,
1172 MVS_CHIP_DISP->phy_work_around(mvi, i);
1175 i + mvi->id * mvi->chip->n_phy, phy->att_dev_info);
1177 i + mvi->id * mvi->chip->n_phy, phy->att_dev_sas_addr);
1180 MVS_CHIP_DISP->write_port_irq_stat(mvi, i, phy->irq_status);
1186 struct mvs_info *mvi = NULL; int i = 0, hi;
1200 mvi = ((struct mvs_prv_info *)sas_ha->lldd_ha)->mvi[hi];
1201 if (i >= mvi->chip->n_phy)
1202 port = &mvi->port[i - mvi->chip->n_phy];
1204 port = &mvi->port[i];
1206 spin_lock_irqsave(&mvi->lock, flags);
1213 mvs_update_wideport(mvi, sas_phy->id);
1217 MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_PHY_STAT);
1218 MVS_CHIP_DISP->write_port_cfg_data(mvi, i, 0x04);
1222 spin_unlock_irqrestore(&mvi->lock, flags);
1229 struct mvs_info *mvi = phy->mvi;
1233 while (phy != &mvi->phy[phy_no]) {
1239 mvs_do_release_task(phy->mvi, phy_no, dev);
1254 struct mvs_device *mvs_alloc_dev(struct mvs_info *mvi)
1258 if (mvi->devices[dev].dev_type == NO_DEVICE) {
1259 mvi->devices[dev].device_id = dev;
1260 return &mvi->devices[dev];
1285 struct mvs_info *mvi = NULL;
1289 mvi = mvs_find_dev_mvi(dev);
1292 spin_lock_irqsave(&mvi->lock, flags);
1294 mvi_device = mvs_alloc_dev(mvi);
1302 mvi_device->mvi_info = mvi;
1328 spin_unlock_irqrestore(&mvi->lock, flags);
1341 struct mvs_info *mvi = mvi_dev->mvi_info;
1343 spin_lock_irqsave(&mvi->lock, flags);
1348 mvs_release_task(mvi, dev);
1349 mvs_free_reg_set(mvi, mvi_dev);
1357 spin_unlock_irqrestore(&mvi->lock, flags);
1493 struct mvs_info *mvi = mvi_dev->mvi_info;
1499 spin_lock_irqsave(&mvi->lock, flags);
1500 mvs_release_task(mvi, dev);
1501 spin_unlock_irqrestore(&mvi->lock, flags);
1514 struct mvs_info *mvi = mvi_dev->mvi_info;
1524 spin_lock_irqsave(&mvi->lock, flags);
1525 mvs_release_task(mvi, dev);
1526 spin_unlock_irqrestore(&mvi->lock, flags);
1542 struct mvs_info *mvi = mvi_dev->mvi_info;
1545 rc = mvs_find_tag(mvi, task, &tag);
1575 struct mvs_info *mvi;
1585 mvi = mvi_dev->mvi_info;
1599 rc = mvs_find_tag(mvi, task, &tag);
1618 slot_no = (u32) (slot - mvi->slot_info);
1619 spin_lock_irqsave(&mvi->lock, flags);
1620 mvs_slot_complete(mvi, slot_no, 1);
1621 spin_unlock_irqrestore(&mvi->lock, flags);
1629 u32 slot_idx = (u32)(slot - mvi->slot_info);
1630 mv_dprintk("mvs_abort_task() mvi=%p task=%p "
1632 mvi, task, slot, slot_idx);
1634 mvs_slot_task_free(mvi, task, slot, slot_idx);
1679 static int mvs_sata_done(struct mvs_info *mvi, struct sas_task *task,
1753 static int mvs_slot_err(struct mvs_info *mvi, struct sas_task *task,
1756 struct mvs_slot_info *slot = &mvi->slot_info[slot_idx];
1764 MVS_CHIP_DISP->issue_stop(mvi, type, tfs);
1766 MVS_CHIP_DISP->command_active(mvi, slot_idx);
1777 sas_ssp_task_response(mvi->dev, task, iu);
1794 mvs_sata_done(mvi, task, slot_idx, err_dw0);
1804 int mvs_slot_complete(struct mvs_info *mvi, u32 rx_desc, u32 flags)
1807 struct mvs_slot_info *slot = &mvi->slot_info[slot_idx];
1840 mvs_free_reg_set(mvi, mvi_dev);
1842 mvs_slot_task_free(mvi, task, slot, slot_idx);
1859 tstat->stat = mvs_slot_err(mvi, task, slot_idx);
1875 sas_ssp_task_response(mvi->dev, task, iu);
1894 tstat->stat = mvs_sata_done(mvi, task, slot_idx, 0);
1912 mvs_free_reg_set(mvi, mvi_dev);
1914 mvs_slot_task_free(mvi, task, slot, slot_idx);
1917 spin_unlock(&mvi->lock);
1921 spin_lock(&mvi->lock);
1926 void mvs_do_release_task(struct mvs_info *mvi,
1934 phy = &mvi->phy[phy_no];
1939 mvs_int_rx(mvi, false);
1945 slot_idx = (u32) (slot - mvi->slot_info);
1953 MVS_CHIP_DISP->command_active(mvi, slot_idx);
1955 mvs_slot_complete(mvi, slot_idx, 1);
1959 void mvs_release_task(struct mvs_info *mvi,
1965 mvs_do_release_task(mvi, phyno[i], dev);
1979 struct mvs_info *mvi = mwq->mvi;
1982 struct sas_ha_struct *sas_ha = mvi->sas;
1983 struct mvs_phy *phy = &mvi->phy[phy_no];
1986 spin_lock_irqsave(&mvi->lock, flags);
1993 tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, phy_no);
2002 MVS_CHIP_DISP->detect_porttype(mvi, phy_no);
2003 mvs_update_phyinfo(mvi, phy_no, 1);
2004 mvs_bytes_dmaed(mvi, phy_no);
2016 spin_unlock_irqrestore(&mvi->lock, flags);
2020 static int mvs_handle_event(struct mvs_info *mvi, void *data, int handler)
2027 mwq->mvi = mvi;
2031 list_add_tail(&mwq->entry, &mvi->wq_list);
2042 struct mvs_info *mvi = phy->mvi;
2045 for (phy_no = 0; phy_no < mvi->chip->n_phy; phy_no++) {
2046 if (&mvi->phy[phy_no] == phy) {
2048 phy_no+mvi->id*mvi->chip->n_phy);
2049 MVS_CHIP_DISP->phy_reset(mvi, phy_no, MVS_HARD_RESET);
2054 void mvs_int_port(struct mvs_info *mvi, int phy_no, u32 events)
2057 struct mvs_phy *phy = &mvi->phy[phy_no];
2059 phy->irq_status = MVS_CHIP_DISP->read_port_irq_stat(mvi, phy_no);
2060 MVS_CHIP_DISP->write_port_irq_stat(mvi, phy_no, phy->irq_status);
2061 mv_dprintk("phy %d ctrl sts=0x%08X.\n", phy_no+mvi->id*mvi->chip->n_phy,
2062 MVS_CHIP_DISP->read_phy_ctl(mvi, phy_no));
2063 mv_dprintk("phy %d irq sts = 0x%08X\n", phy_no+mvi->id*mvi->chip->n_phy,
2073 phy_no + mvi->id*mvi->chip->n_phy);
2081 mvs_do_release_task(mvi, phy_no, NULL);
2083 MVS_CHIP_DISP->clear_srs_irq(mvi, 0, 1);
2084 mvs_handle_event(mvi,
2087 ready = mvs_is_phy_ready(mvi, phy_no);
2090 MVS_CHIP_DISP->stp_reset(mvi,
2093 MVS_CHIP_DISP->phy_reset(mvi,
2101 tmp = MVS_CHIP_DISP->read_port_irq_mask(mvi, phy_no);
2102 MVS_CHIP_DISP->write_port_irq_mask(mvi, phy_no,
2112 phy->phy_status = mvs_is_phy_ready(mvi, phy_no);
2116 MVS_CHIP_DISP->detect_porttype(mvi, phy_no);
2119 mvi, phy_no);
2121 MVS_CHIP_DISP->write_port_irq_mask(mvi,
2124 mvs_update_phyinfo(mvi, phy_no, 0);
2126 MVS_CHIP_DISP->phy_reset(mvi, phy_no, MVS_PHY_TUNE);
2130 mvs_bytes_dmaed(mvi, phy_no);
2138 phy_no + mvi->id*mvi->chip->n_phy);
2142 phy_no + mvi->id*mvi->chip->n_phy);
2143 mvs_handle_event(mvi, (void *)(unsigned long)phy_no,
2148 int mvs_int_rx(struct mvs_info *mvi, bool self_clear)
2158 rx_prod_idx = mvi->rx_cons;
2159 mvi->rx_cons = le32_to_cpu(mvi->rx[0]);
2160 if (mvi->rx_cons == 0xfff) /* h/w hasn't touched RX ring yet */
2167 if (unlikely(mvi->rx_cons == rx_prod_idx))
2168 mvi->rx_cons = MVS_CHIP_DISP->rx_update(mvi) & RX_RING_SZ_MASK;
2170 if (mvi->rx_cons == rx_prod_idx)
2173 while (mvi->rx_cons != rx_prod_idx) {
2176 rx_desc = le32_to_cpu(mvi->rx[rx_prod_idx + 1]);
2179 mvs_slot_complete(mvi, rx_desc, 0);
2184 mvs_slot_complete(mvi, rx_desc, 0);
2186 mvs_slot_free(mvi, rx_desc);
2191 MVS_CHIP_DISP->int_full(mvi);