Cross Reference: /drivers/spi/spi-imx.c

Lines Matching refs:base
86 	void __iomem *base;
120 	unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA);	\
140 	writel(val, spi_imx->base + MXC_CSPITXDATA);			\
226 		pr_err("%s: cannot set clock freq: %u (base freq: %u)\n",
249 	writel(val, spi_imx->base + MX51_ECSPI_INT);
256 	reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
258 	writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
294 	writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
295 	writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
302 	return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR;
309 		readl(spi_imx->base + MXC_CSPIRXDATA);
344 	writel(val, spi_imx->base + MXC_CSPIINT);
351 	reg = readl(spi_imx->base + MXC_CSPICTRL);
353 	writel(reg, spi_imx->base + MXC_CSPICTRL);
383 	writel(reg, spi_imx->base + MXC_CSPICTRL);
390 	return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
396 	while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR)
397 		readl(spi_imx->base + MXC_CSPIRXDATA);
422 	writel(val, spi_imx->base + MXC_CSPIINT);
429 	reg = readl(spi_imx->base + MXC_CSPICTRL);
431 	writel(reg, spi_imx->base + MXC_CSPICTRL);
454 	writel(reg, spi_imx->base + MXC_CSPICTRL);
461 	return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR;
466 	writel(1, spi_imx->base + MXC_RESET);
489 	writel(val, spi_imx->base + MXC_CSPIINT);
496 	reg = readl(spi_imx->base + MXC_CSPICTRL);
498 	writel(reg, spi_imx->base + MXC_CSPICTRL);
515 	writel(reg, spi_imx->base + MXC_CSPICTRL);
522 	return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
527 	writel(1, spi_imx->base + MXC_RESET);
830 	spi_imx->base = ioremap(res->start, resource_size(res));
831 	if (!spi_imx->base) {
879 	iounmap(spi_imx->base);
902 	writel(0, spi_imx->base + MXC_CSPICTRL);
906 	iounmap(spi_imx->base);