Cross Reference: /drivers/staging/vme/bridges/vme

Lines Matching refs:bridge
78 static u32 tsi148_DMA_irqhandler(struct tsi148_driver *bridge,
84 		wake_up(&bridge->dma_queue[0]);
88 		wake_up(&bridge->dma_queue[1]);
98 static u32 tsi148_LM_irqhandler(struct tsi148_driver *bridge, u32 stat)
106 			bridge->lm_callback[i](i);
124 	struct tsi148_driver *bridge;
126 	bridge = tsi148_bridge->driver_priv;
130 			val = ioread32be(bridge->base +	TSI148_GCSR_MBOX[i]);
145 	struct tsi148_driver *bridge;
147 	bridge = tsi148_bridge->driver_priv;
151 		ioread32be(bridge->base + TSI148_LCSR_EDPAU),
152 		ioread32be(bridge->base + TSI148_LCSR_EDPAL),
153 		ioread32be(bridge->base + TSI148_LCSR_EDPAT));
157 		ioread32be(bridge->base + TSI148_LCSR_EDPXA),
158 		ioread32be(bridge->base + TSI148_LCSR_EDPXS));
160 	iowrite32be(TSI148_LCSR_EDPAT_EDPCL, bridge->base + TSI148_LCSR_EDPAT);
174 	struct tsi148_driver *bridge;
176 	bridge = tsi148_bridge->driver_priv;
178 	error_addr_high = ioread32be(bridge->base + TSI148_LCSR_VEAU);
179 	error_addr_low = ioread32be(bridge->base + TSI148_LCSR_VEAL);
180 	error_attrib = ioread32be(bridge->base + TSI148_LCSR_VEAT);
203 	iowrite32be(TSI148_LCSR_VEAT_VESCL, bridge->base + TSI148_LCSR_VEAT);
211 static u32 tsi148_IACK_irqhandler(struct tsi148_driver *bridge)
213 	wake_up(&bridge->iack_queue);
225 	struct tsi148_driver *bridge;
227 	bridge = tsi148_bridge->driver_priv;
236 			vec = ioread8(bridge->base + TSI148_LCSR_VIACK[i] + 3);
255 	struct tsi148_driver *bridge;
259 	bridge = tsi148_bridge->driver_priv;
262 	enable = ioread32be(bridge->base + TSI148_LCSR_INTEO);
263 	stat = ioread32be(bridge->base + TSI148_LCSR_INTS);
274 		serviced |= tsi148_DMA_irqhandler(bridge, stat);
279 		serviced |= tsi148_LM_irqhandler(bridge, stat);
296 		serviced |= tsi148_IACK_irqhandler(bridge);
306 	iowrite32be(serviced, bridge->base + TSI148_LCSR_INTC);
316 	struct tsi148_driver *bridge;
320 	bridge = tsi148_bridge->driver_priv;
371 	iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
372 	iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
380 	struct tsi148_driver *bridge = tsi148_bridge->driver_priv;
383 	iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEO);
384 	iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEN);
387 	iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_INTC);
396 static int tsi148_iack_received(struct tsi148_driver *bridge)
400 	tmp = ioread32be(bridge->base + TSI148_LCSR_VICR);
416 	struct tsi148_driver *bridge;
418 	bridge = tsi148_bridge->driver_priv;
422 		tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);
424 		iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
426 		tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
428 		iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
437 		tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
439 		iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
441 		tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);
443 		iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
455 	struct tsi148_driver *bridge;
457 	bridge = tsi148_bridge->driver_priv;
459 	mutex_lock(&bridge->vme_int);
462 	tmp = ioread32be(bridge->base + TSI148_LCSR_VICR);
467 	iowrite32be(tmp, bridge->base + TSI148_LCSR_VICR);
471 	iowrite32be(tmp, bridge->base + TSI148_LCSR_VICR);
474 	wait_event_interruptible(bridge->iack_queue,
475 		tsi148_iack_received(bridge));
477 	mutex_unlock(&bridge->vme_int);
563 	struct tsi148_driver *bridge;
566 	bridge = tsi148_bridge->driver_priv;
625 	temp_ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
628 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +
632 	iowrite32be(vme_base_high, bridge->base + TSI148_LCSR_IT[i] +
634 	iowrite32be(vme_base_low, bridge->base + TSI148_LCSR_IT[i] +
636 	iowrite32be(vme_bound_high, bridge->base + TSI148_LCSR_IT[i] +
638 	iowrite32be(vme_bound_low, bridge->base + TSI148_LCSR_IT[i] +
640 	iowrite32be(pci_offset_high, bridge->base + TSI148_LCSR_IT[i] +
642 	iowrite32be(pci_offset_low, bridge->base + TSI148_LCSR_IT[i] +
687 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +
693 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +
711 	struct tsi148_driver *bridge;
713 	bridge = image->parent->driver_priv;
718 	ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
721 	vme_base_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
723 	vme_base_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
725 	vme_bound_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
727 	vme_bound_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
729 	pci_offset_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
731 	pci_offset_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
907 	struct tsi148_driver *bridge;
911 	bridge = tsi148_bridge->driver_priv;
985 	temp_ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
988 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +
1090 	iowrite32be(pci_base_high, bridge->base + TSI148_LCSR_OT[i] +
1092 	iowrite32be(pci_base_low, bridge->base + TSI148_LCSR_OT[i] +
1094 	iowrite32be(pci_bound_high, bridge->base + TSI148_LCSR_OT[i] +
1096 	iowrite32be(pci_bound_low, bridge->base + TSI148_LCSR_OT[i] +
1098 	iowrite32be(vme_offset_high, bridge->base + TSI148_LCSR_OT[i] +
1100 	iowrite32be(vme_offset_low, bridge->base + TSI148_LCSR_OT[i] +
1104 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +
1110 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +
1141 	struct tsi148_driver *bridge;
1143 	bridge = image->parent->driver_priv;
1147 	ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1150 	pci_base_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1152 	pci_base_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1154 	pci_bound_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1156 	pci_bound_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1158 	vme_offset_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1160 	vme_offset_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1306 	struct tsi148_driver *bridge;
1310 	bridge = tsi148_bridge->driver_priv;
1338 	ioread16(bridge->flush_image->kern_base + 0x7F000);
1370 	struct tsi148_driver *bridge;
1372 	bridge = image->parent->driver_priv;
1378 	mutex_lock(&bridge->vme_rmw);
1383 	pci_addr_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1385 	pci_addr_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1392 	iowrite32be(mask, bridge->base + TSI148_LCSR_RMWEN);
1393 	iowrite32be(compare, bridge->base + TSI148_LCSR_RMWC);
1394 	iowrite32be(swap, bridge->base + TSI148_LCSR_RMWS);
1395 	iowrite32be(pci_addr_high, bridge->base + TSI148_LCSR_RMWAU);
1396 	iowrite32be(pci_addr_low, bridge->base + TSI148_LCSR_RMWAL);
1399 	tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL);
1401 	iowrite32be(tmp, bridge->base + TSI148_LCSR_VMCTRL);
1407 	tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL);
1409 	iowrite32be(tmp, bridge->base + TSI148_LCSR_VMCTRL);
1413 	mutex_unlock(&bridge->vme_rmw);
1763 	struct tsi148_driver *bridge;
1765 	bridge = tsi148_bridge->driver_priv;
1767 	tmp = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] +
1791 	struct tsi148_driver *bridge;
1797 	bridge = tsi148_bridge->driver_priv;
1826 	iowrite32be(bus_addr_high, bridge->base +
1828 	iowrite32be(bus_addr_low, bridge->base +
1832 	iowrite32be(dctlreg | TSI148_LCSR_DCTL_DGO, bridge->base +
1835 	wait_event_interruptible(bridge->dma_queue[channel],
1841 	val = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] +
1890 	struct tsi148_driver *bridge;
1894 	bridge = tsi148_bridge->driver_priv;
1900 		if (bridge->lm_callback[i] != NULL) {
1939 	iowrite32be(lm_base_high, bridge->base + TSI148_LCSR_LMBAU);
1940 	iowrite32be(lm_base_low, bridge->base + TSI148_LCSR_LMBAL);
1941 	iowrite32be(lm_ctl, bridge->base + TSI148_LCSR_LMAT);
1955 	struct tsi148_driver *bridge;
1957 	bridge = lm->parent->driver_priv;
1961 	lm_base_high = ioread32be(bridge->base + TSI148_LCSR_LMBAU);
1962 	lm_base_low = ioread32be(bridge->base + TSI148_LCSR_LMBAL);
1963 	lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT);
2007 	struct tsi148_driver *bridge;
2011 	bridge = tsi148_bridge->driver_priv;
2016 	lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT);
2025 	if (bridge->lm_callback[monitor] != NULL) {
2032 	bridge->lm_callback[monitor] = callback;
2035 	tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);
2037 	iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
2039 	tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
2041 	iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
2046 		iowrite32be(lm_ctl, bridge->base + TSI148_LCSR_LMAT);
2060 	struct tsi148_driver *bridge;
2062 	bridge = lm->parent->driver_priv;
2067 	lm_en = ioread32be(bridge->base + TSI148_LCSR_INTEN);
2069 	iowrite32be(lm_en, bridge->base + TSI148_LCSR_INTEN);
2071 	tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
2073 	iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
2076 		 bridge->base + TSI148_LCSR_INTC);
2079 	bridge->lm_callback[monitor] = NULL;
2084 		tmp = ioread32be(bridge->base + TSI148_LCSR_LMAT);
2086 		iowrite32be(tmp, bridge->base + TSI148_LCSR_LMAT);
2100 	struct tsi148_driver *bridge;
2102 	bridge = tsi148_bridge->driver_priv;
2105 		slot = ioread32be(bridge->base + TSI148_LCSR_VSTAT);
2158 	struct tsi148_driver *bridge;
2160 	bridge = tsi148_bridge->driver_priv;
2163 	bridge->crcsr_kernel = pci_alloc_consistent(pdev, VME_CRCSR_BUF_SIZE,
2164 		&bridge->crcsr_bus);
2165 	if (bridge->crcsr_kernel == NULL) {
2171 	memset(bridge->crcsr_kernel, 0, VME_CRCSR_BUF_SIZE);
2173 	reg_split(bridge->crcsr_bus, &crcsr_bus_high, &crcsr_bus_low);
2175 	iowrite32be(crcsr_bus_high, bridge->base + TSI148_LCSR_CROU);
2176 	iowrite32be(crcsr_bus_low, bridge->base + TSI148_LCSR_CROL);
2179 	cbar = ioread32be(bridge->base + TSI148_CBAR);
2187 		iowrite32be(cbar<<3, bridge->base + TSI148_CBAR);
2191 	crat = ioread32be(bridge->base + TSI148_LCSR_CRAT);
2195 			bridge->base + TSI148_LCSR_CRAT);
2204 		retval = tsi148_master_set(bridge->flush_image, 1,
2220 	struct tsi148_driver *bridge;
2222 	bridge = tsi148_bridge->driver_priv;
2225 	crat = ioread32be(bridge->base + TSI148_LCSR_CRAT);
2227 		bridge->base + TSI148_LCSR_CRAT);
2230 	iowrite32be(0, bridge->base + TSI148_LCSR_CROU);
2231 	iowrite32be(0, bridge->base + TSI148_LCSR_CROL);
2233 	pci_free_consistent(pdev, VME_CRCSR_BUF_SIZE, bridge->crcsr_kernel,
2234 		bridge->crcsr_bus);
2249 	/* If we want to support more than one of each bridge, we need to
2559 	struct tsi148_driver *bridge;
2562 	bridge = tsi148_bridge->driver_priv;
2571 		iowrite32be(0, bridge->base + TSI148_LCSR_IT[i] +
2573 		iowrite32be(0, bridge->base + TSI148_LCSR_OT[i] +
2580 	iowrite32be(0, bridge->base + TSI148_LCSR_LMAT);
2585 	iowrite32be(0, bridge->base + TSI148_LCSR_CSRAT);
2590 	iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_EDPAT);
2591 	iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_VEAT);
2592 	iowrite32be(0x07000700, bridge->base + TSI148_LCSR_PSTAT);
2597 	if (ioread32be(bridge->base + TSI148_LCSR_VICR) & 0x800)
2598 		iowrite32be(0x8000, bridge->base + TSI148_LCSR_VICR);
2603 	iowrite32be(0x0, bridge->base + TSI148_LCSR_INTM1);
2604 	iowrite32be(0x0, bridge->base + TSI148_LCSR_INTM2);
2634 	iounmap(bridge->base);
2656 MODULE_DESCRIPTION("VME driver for the Tundra Tempe VME bridge");