Lines Matching refs:tmp
214 u32 tmp;
217 tmp = AMD_BIT(UDC_DEVINT_SVC) |
225 writel(tmp, &dev->regs->irqmsk);
236 u32 tmp;
241 tmp = readl(&dev->regs->ep_irqmsk);
243 tmp &= AMD_UNMASK_BIT(UDC_EPINT_IN_EP0)
245 writel(tmp, &dev->regs->ep_irqmsk);
253 u32 tmp;
258 tmp = readl(&dev->regs->irqmsk);
261 tmp &= AMD_UNMASK_BIT(UDC_DEVINT_SI)
266 writel(tmp, &dev->regs->irqmsk);
275 u32 tmp;
288 tmp = readl(&dev->ep[i].regs->bufin_framenum);
289 tmp = AMD_GETBITS(tmp, UDC_EPIN_BUFF_SIZE);
290 ep->txfifo += tmp;
316 u32 tmp;
341 tmp = readl(&dev->ep[ep->num].regs->ctl);
342 tmp = AMD_ADDBITS(tmp, desc->bmAttributes, UDC_EPCTL_ET);
343 writel(tmp, &dev->ep[ep->num].regs->ctl);
347 tmp = readl(&dev->ep[ep->num].regs->bufout_maxpkt);
348 tmp = AMD_ADDBITS(tmp, maxpacket, UDC_EP_MAX_PKT_SIZE);
350 writel(tmp, &dev->ep[ep->num].regs->bufout_maxpkt);
359 tmp = readl(&dev->ep[ep->num].regs->bufin_framenum);
361 tmp = AMD_ADDBITS(
362 tmp,
366 writel(tmp, &dev->ep[ep->num].regs->bufin_framenum);
372 tmp = readl(&ep->regs->ctl);
373 tmp |= AMD_BIT(UDC_EPCTL_F);
374 writel(tmp, &ep->regs->ctl);
382 tmp = readl(&dev->csr->ne[ep->num - UDC_CSR_EP_OUT_IX_OFS]);
383 tmp = AMD_ADDBITS(tmp, maxpacket,
385 writel(tmp, &dev->csr->ne[ep->num - UDC_CSR_EP_OUT_IX_OFS]);
398 tmp = readl(&dev->csr->ne[udc_csr_epix]);
400 tmp = AMD_ADDBITS(tmp, maxpacket, UDC_CSR_NE_MAX_PKT);
402 tmp = AMD_ADDBITS(tmp, desc->bEndpointAddress, UDC_CSR_NE_NUM);
404 tmp = AMD_ADDBITS(tmp, ep->in, UDC_CSR_NE_DIR);
406 tmp = AMD_ADDBITS(tmp, desc->bmAttributes, UDC_CSR_NE_TYPE);
408 tmp = AMD_ADDBITS(tmp, ep->dev->cur_config, UDC_CSR_NE_CFG);
410 tmp = AMD_ADDBITS(tmp, ep->dev->cur_intf, UDC_CSR_NE_INTF);
412 tmp = AMD_ADDBITS(tmp, ep->dev->cur_alt, UDC_CSR_NE_ALT);
414 writel(tmp, &dev->csr->ne[udc_csr_epix]);
417 tmp = readl(&dev->regs->ep_irqmsk);
418 tmp &= AMD_UNMASK_BIT(ep->num);
419 writel(tmp, &dev->regs->ep_irqmsk);
426 tmp = readl(&ep->regs->ctl);
427 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
428 writel(tmp, &ep->regs->ctl);
432 tmp = desc->bEndpointAddress;
442 u32 tmp;
452 tmp = readl(&ep->regs->ctl);
453 tmp |= AMD_BIT(UDC_EPCTL_SNAK);
454 writel(tmp, &ep->regs->ctl);
458 tmp = readl(®s->ep_irqmsk);
459 tmp |= AMD_BIT(ep->num);
460 writel(tmp, ®s->ep_irqmsk);
464 tmp = readl(&ep->regs->ctl);
465 tmp &= AMD_UNMASK_BIT(UDC_EPCTL_P);
466 writel(tmp, &ep->regs->ctl);
468 tmp = readl(&ep->regs->sts);
469 tmp |= AMD_BIT(UDC_EPSTS_IN);
470 writel(tmp, &ep->regs->sts);
473 tmp = readl(&ep->regs->ctl);
474 tmp |= AMD_BIT(UDC_EPCTL_F);
475 writel(tmp, &ep->regs->ctl);
669 u32 tmp;
679 tmp = readl(dev->rxfifo);
681 *(buf + (i<<2) + j) = (u8)(tmp & UDC_BYTE_MASK);
682 tmp = tmp >> UDC_BITS_PER_BYTE;
731 u32 tmp;
804 tmp = readl(&ep->regs->ctl);
805 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
806 writel(tmp, &ep->regs->ctl);
1035 u32 tmp;
1044 tmp = readl(&dev->regs->ctl);
1045 tmp |= AMD_BIT(UDC_DEVCTL_RDE);
1046 writel(tmp, &dev->regs->ctl);
1059 u32 tmp;
1107 tmp = readl(&dev->regs->ctl);
1108 tmp |= AMD_BIT(UDC_DEVCTL_CSR_DONE);
1109 writel(tmp, &dev->regs->ctl);
1115 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
1116 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1117 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
1146 tmp = readl(&dev->regs->ctl);
1147 tmp &= AMD_UNMASK_BIT(UDC_DEVCTL_RDE);
1148 writel(tmp, &dev->regs->ctl);
1167 tmp = readl(&ep->regs->ctl);
1168 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1169 writel(tmp, &ep->regs->ctl);
1176 tmp = readl(&dev->regs->ep_irqmsk);
1177 tmp &= AMD_UNMASK_BIT(ep->num);
1178 writel(tmp, &dev->regs->ep_irqmsk);
1182 tmp = readl(&dev->regs->ep_irqmsk);
1183 tmp &= AMD_UNMASK_BIT(ep->num);
1184 writel(tmp, &dev->regs->ep_irqmsk);
1275 u32 tmp;
1278 tmp = readl(&udc->regs->ctl);
1279 writel(tmp & AMD_UNMASK_BIT(UDC_DEVCTL_RDE),
1294 writel(tmp, &udc->regs->ctl);
1310 u32 tmp;
1335 tmp = readl(&ep->regs->ctl);
1336 tmp |= AMD_BIT(UDC_EPCTL_S);
1337 writel(tmp, &ep->regs->ctl);
1354 tmp = readl(&ep->regs->ctl);
1356 tmp = tmp & AMD_CLEAR_BIT(UDC_EPCTL_S);
1358 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1359 writel(tmp, &ep->regs->ctl);
1439 u32 tmp;
1453 tmp = readl(&dev->regs->cfg);
1455 tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_FS, UDC_DEVCFG_SPD);
1457 tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_HS, UDC_DEVCFG_SPD);
1458 writel(tmp, &dev->regs->cfg);
1466 u32 tmp;
1481 tmp = readl(&dev->regs->ctl);
1482 tmp &= AMD_UNMASK_BIT(UDC_DEVCTL_RDE);
1483 tmp &= AMD_UNMASK_BIT(UDC_DEVCTL_TDE);
1484 writel(tmp, &dev->regs->ctl);
1487 tmp = readl(&dev->regs->cfg);
1488 tmp |= AMD_BIT(UDC_DEVCFG_CSR_PRG);
1490 tmp |= AMD_BIT(UDC_DEVCFG_SP);
1492 tmp |= AMD_BIT(UDC_DEVCFG_RWKP);
1493 writel(tmp, &dev->regs->cfg);
1505 u32 tmp;
1511 tmp = readl(&dev->regs->sts);
1512 tmp = AMD_GETBITS(tmp, UDC_DEVSTS_ENUM_SPEED);
1513 if (tmp == UDC_DEVSTS_ENUM_SPEED_HIGH)
1515 else if (tmp == UDC_DEVSTS_ENUM_SPEED_FULL)
1519 for (tmp = 0; tmp < UDC_EP_NUM; tmp++) {
1520 ep = &dev->ep[tmp];
1522 ep->ep.name = ep_string[tmp];
1523 ep->num = tmp;
1528 if (tmp < UDC_EPIN_NUM) {
1536 ep->regs = &dev->ep_regs[tmp];
1554 if (tmp != UDC_EP0IN_IX && tmp != UDC_EP0OUT_IX
1555 && tmp > UDC_EPIN_NUM) {
1557 reg = readl(&dev->ep[tmp].regs->ctl);
1559 writel(reg, &dev->ep[tmp].regs->ctl);
1560 dev->ep[tmp].naking = 1;
1630 u32 tmp;
1641 for (tmp = 0; tmp < UDC_EP_NUM; tmp++)
1642 empty_req_queue(&dev->ep[tmp]);
1661 tmp = readl(&dev->regs->cfg);
1662 tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_FS, UDC_DEVCFG_SPD);
1663 writel(tmp, &dev->regs->cfg);
1694 u32 tmp;
1705 tmp = readl(&udc->regs->ctl);
1706 tmp |= AMD_BIT(UDC_DEVCTL_RDE);
1707 writel(tmp, &udc->regs->ctl);
1744 u32 tmp;
1747 tmp = readl(&ep->regs->ctl);
1749 if (!(tmp & AMD_BIT(UDC_EPCTL_S))) {
1759 tmp |= AMD_BIT(UDC_EPCTL_S);
1760 writel(tmp, &ep->regs->ctl);*/
1763 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1764 writel(tmp, &ep->regs->ctl);
1808 u32 tmp;
1813 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
1814 tmp |= AMD_BIT(UDC_EPCTL_F);
1815 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
1822 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->bufin_framenum);
1824 tmp = AMD_ADDBITS(tmp, UDC_FS_EPIN0_BUFF_SIZE,
1827 tmp = AMD_ADDBITS(tmp, UDC_EPIN0_BUFF_SIZE,
1829 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->bufin_framenum);
1832 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->bufout_maxpkt);
1834 tmp = AMD_ADDBITS(tmp, UDC_FS_EP0IN_MAX_PKT_SIZE,
1837 tmp = AMD_ADDBITS(tmp, UDC_EP0IN_MAX_PKT_SIZE,
1839 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->bufout_maxpkt);
1842 tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->bufout_maxpkt);
1844 tmp = AMD_ADDBITS(tmp, UDC_FS_EP0OUT_MAX_PKT_SIZE,
1847 tmp = AMD_ADDBITS(tmp, UDC_EP0OUT_MAX_PKT_SIZE,
1849 writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->bufout_maxpkt);
1852 tmp = readl(&dev->csr->ne[0]);
1854 tmp = AMD_ADDBITS(tmp, UDC_FS_EP0OUT_MAX_PKT_SIZE,
1857 tmp = AMD_ADDBITS(tmp, UDC_EP0OUT_MAX_PKT_SIZE,
1859 writel(tmp, &dev->csr->ne[0]);
1878 tmp = readl(&dev->regs->ctl);
1879 tmp |= AMD_BIT(UDC_DEVCTL_MODE)
1883 tmp |= AMD_BIT(UDC_DEVCTL_BF);
1885 tmp |= AMD_BIT(UDC_DEVCTL_DU);
1886 writel(tmp, &dev->regs->ctl);
1890 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
1891 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1892 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
1897 tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl);
1898 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1899 writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->ctl);
1922 u32 tmp;
1956 tmp = readl(&dev->regs->ctl);
1957 tmp = tmp & AMD_CLEAR_BIT(UDC_DEVCTL_SD);
1958 writel(tmp, &dev->regs->ctl);
1971 int tmp;
1981 for (tmp = 0; tmp < UDC_EP_NUM; tmp++)
1982 empty_req_queue(&dev->ep[tmp]);
1992 u32 tmp;
2009 tmp = readl(&dev->regs->ctl);
2010 tmp |= AMD_BIT(UDC_DEVCTL_SD);
2011 writel(tmp, &dev->regs->ctl);
2022 u32 tmp;
2027 for (tmp = 0; tmp < UDC_EPIN_NUM_USED; tmp++) {
2028 if (cnak_pending & (1 << tmp)) {
2029 DBG(dev, "CNAK pending for ep%d\n", tmp);
2031 reg = readl(&dev->ep[tmp].regs->ctl);
2033 writel(reg, &dev->ep[tmp].regs->ctl);
2034 dev->ep[tmp].naking = 0;
2035 UDC_QUEUE_CNAK(&dev->ep[tmp], dev->ep[tmp].num);
2082 u32 tmp;
2092 tmp = readl(&ep->regs->sts);
2095 if (tmp & AMD_BIT(UDC_EPSTS_BNA)) {
2099 writel(tmp | AMD_BIT(UDC_EPSTS_BNA), &ep->regs->sts);
2109 if (tmp & AMD_BIT(UDC_EPSTS_HE)) {
2113 writel(tmp | AMD_BIT(UDC_EPSTS_HE), &ep->regs->sts);
2200 tmp = req->req.length - req->req.actual;
2201 if (count > tmp) {
2202 if ((tmp % ep->ep.maxpacket) != 0) {
2204 ep->ep.name, count, tmp);
2207 count = tmp;
2296 u32 tmp;
2365 tmp = readl(&dev->regs->ep_irqmsk);
2366 tmp |= AMD_BIT(ep->num);
2367 writel(tmp, &dev->regs->ep_irqmsk);
2428 tmp = readl(&ep->regs->ctl);
2429 tmp |= AMD_BIT(UDC_EPCTL_P);
2430 writel(tmp, &ep->regs->ctl);
2436 tmp = readl(
2438 tmp |= AMD_BIT(ep->num);
2439 writel(tmp,
2457 u32 tmp;
2469 tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->sts);
2471 if (tmp & AMD_BIT(UDC_EPSTS_BNA)) {
2481 tmp = AMD_GETBITS(tmp, UDC_EPSTS_OUT);
2482 VDBG(dev, "data_typ = %x\n", tmp);
2485 if (tmp == UDC_EPSTS_OUT_SETUP) {
2492 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
2493 tmp |= AMD_BIT(UDC_EPCTL_SNAK);
2494 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
2574 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
2579 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
2580 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
2586 tmp |= AMD_BIT(UDC_EPCTL_S);
2587 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
2594 tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl);
2595 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
2596 writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->ctl);
2608 } else if (tmp == UDC_EPSTS_OUT_DATA) {
2671 u32 tmp;
2681 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->sts);
2683 if (tmp & AMD_BIT(UDC_EPSTS_TDC)) {
2692 } else if (tmp & AMD_BIT(UDC_EPSTS_IN)) {
2703 tmp = readl(&ep->regs->ctl);
2704 tmp |= AMD_BIT(UDC_EPCTL_S);
2705 writel(tmp, &ep->regs->ctl);
2723 tmp =
2725 tmp |= AMD_BIT(UDC_EPCTL_P);
2726 writel(tmp,
2773 u32 tmp;
2784 tmp = readl(&dev->regs->sts);
2785 cfg = AMD_GETBITS(tmp, UDC_DEVSTS_CFG);
2810 tmp = readl(&dev->csr->ne[udc_csr_epix]);
2812 tmp = AMD_ADDBITS(tmp, ep->dev->cur_config,
2815 writel(tmp, &dev->csr->ne[udc_csr_epix]);
2819 tmp = readl(&ep->regs->ctl);
2820 tmp = tmp & AMD_CLEAR_BIT(UDC_EPCTL_S);
2821 writel(tmp, &ep->regs->ctl);
2825 tmp = dev->driver->setup(&dev->gadget, &setup_data.request);
2834 tmp = readl(&dev->regs->sts);
2835 dev->cur_alt = AMD_GETBITS(tmp, UDC_DEVSTS_ALT);
2836 dev->cur_intf = AMD_GETBITS(tmp, UDC_DEVSTS_INTF);
2865 tmp = readl(&dev->csr->ne[udc_csr_epix]);
2867 tmp = AMD_ADDBITS(tmp, ep->dev->cur_intf,
2869 /* tmp = AMD_ADDBITS(tmp, 2, UDC_CSR_NE_INTF); */
2871 tmp = AMD_ADDBITS(tmp, ep->dev->cur_alt,
2874 writel(tmp, &dev->csr->ne[udc_csr_epix]);
2878 tmp = readl(&ep->regs->ctl);
2879 tmp = tmp & AMD_CLEAR_BIT(UDC_EPCTL_S);
2880 writel(tmp, &ep->regs->ctl);
2885 tmp = dev->driver->setup(&dev->gadget, &setup_data.request);
2916 tmp = readl(&dev->regs->sts);
2917 if (!(tmp & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY))
2929 tmp = readl(&dev->regs->cfg);
2930 writel(tmp | AMD_BIT(UDC_DEVCFG_DMARST), &dev->regs->cfg);
2931 writel(tmp, &dev->regs->cfg);
2940 tmp = readl(&dev->regs->irqmsk);
2941 tmp &= AMD_UNMASK_BIT(UDC_DEVINT_US);
2942 writel(tmp, &dev->regs->irqmsk);
2981 tmp = readl(&dev->regs->sts);
2982 if (!(tmp & AMD_BIT(UDC_DEVSTS_SESSVLD))) {
2984 tmp = readl(&dev->regs->irqmsk);
2985 tmp |= AMD_BIT(UDC_DEVINT_US);
2986 writel(tmp, &dev->regs->irqmsk);
3296 char tmp[128];
3317 snprintf(tmp, sizeof tmp, "%d", dev->irq);
3320 tmp, dev->phys_addr, dev->chiprev,
3322 strcpy(tmp, UDC_DRIVER_VERSION_STRING);
3329 "driver version: %s(for Geode5536 B1)\n", tmp);
3370 u32 tmp;
3376 tmp = readl(&dev->regs->ctl);
3377 tmp |= AMD_BIT(UDC_DEVCTL_RES);
3378 writel(tmp, &dev->regs->ctl);
3379 tmp &= AMD_CLEAR_BIT(UDC_DEVCTL_RES);
3380 writel(tmp, &dev->regs->ctl);