Cross Reference: /drivers/video/exynos/exynos_dp

Lines Matching refs:lane
241 					int pre_emphasis, int lane)
243 	switch (lane) {
264 	int lane;
272 	for (lane = 0; lane < lane_count; lane++)
273 		dp->link_train.cr_loop[lane] = 0;
290 	for (lane = 0; lane < lane_count; lane++)
292 			PRE_EMPHASIS_LEVEL_0, lane);
303 	for (lane = 0; lane < lane_count; lane++)
304 		buf[lane] = DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 |
311 static unsigned char exynos_dp_get_lane_status(u8 link_status[6], int lane)
313 	int shift = (lane & 1) * 4;
314 	u8 link_value = link_status[lane>>1];
321 	int lane;
324 	for (lane = 0; lane < lane_count; lane++) {
325 		lane_status = exynos_dp_get_lane_status(link_status, lane);
334 	int lane;
342 	for (lane = 0; lane < lane_count; lane++) {
343 		lane_status = exynos_dp_get_lane_status(link_status, lane);
352 							int lane)
354 	int shift = (lane & 1) * 4;
355 	u8 link_value = adjust_request[lane>>1];
362 					int lane)
364 	int shift = (lane & 1) * 4;
365 	u8 link_value = adjust_request[lane>>1];
371 					u8 training_lane_set, int lane)
373 	switch (lane) {
393 				int lane)
397 	switch (lane) {
434 	int lane;
441 	for (lane = 0; lane < lane_count; lane++) {
443 						adjust_request, lane);
445 						adjust_request, lane);
454 		dp->link_train.training_lane[lane] = training_lane;
461 	int lane;
465 	for (lane = 0; lane < lane_count; lane++) {
467 			dp->link_train.cr_loop[lane] == MAX_CR_LOOP)
477 	int lane;
507 		for (lane = 0; lane < lane_count; lane++) {
509 				dp->link_train.training_lane[lane],
510 				lane);
511 			buf[lane] = dp->link_train.training_lane[lane];
513 				DPCD_ADDR_TRAINING_LANE0_SET + lane,
514 				buf[lane]);
528 		for (lane = 0; lane < lane_count; lane++) {
530 							dp, lane);
532 							adjust_request, lane);
534 							adjust_request, lane);
537 				dp->link_train.cr_loop[lane]++;
538 			dp->link_train.training_lane[lane] = training_lane;
546 			for (lane = 0; lane < lane_count; lane++) {
548 					dp->link_train.training_lane[lane],
549 					lane);
550 				buf[lane] = dp->link_train.training_lane[lane];
552 					DPCD_ADDR_TRAINING_LANE0_SET + lane,
553 					buf[lane]);
564 	int lane;
594 			dev_dbg(dp->dev, "final lane count = %.2x\n",
609 				for (lane = 0; lane < lane_count; lane++) {
611 						dp->link_train.training_lane[lane],
612 						lane);
613 					buf[lane] = dp->link_train.training_lane[lane];
615 						DPCD_ADDR_TRAINING_LANE0_SET + lane,
616 						buf[lane]);
647 	 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
680 	/* Setup TX lane count & rate */
695 	/* Turn off unnecessary lane */