Cross Reference: /drivers/video/matrox/matroxfb

Lines Matching refs:hw
94 	minfo->hw.DACclk[0] = m;
95 	minfo->hw.DACclk[1] = n;
96 	minfo->hw.DACclk[2] = p;
103 	struct matrox_hw_state *hw = &minfo->hw;
109 		hw->DACclk[3] = inDAC1064(minfo, DAC1064_XSYSPLLM);
110 		hw->DACclk[4] = inDAC1064(minfo, DAC1064_XSYSPLLN);
111 		hw->DACclk[5] = inDAC1064(minfo, DAC1064_XSYSPLLP);
114 	mx = hw->MXoptionReg | 0x00000004;
142 		outDAC1064(minfo, DAC1064_XSYSPLLM, hw->DACclk[3] = m);
143 		outDAC1064(minfo, DAC1064_XSYSPLLN, hw->DACclk[4] = n);
144 		outDAC1064(minfo, DAC1064_XSYSPLLP, hw->DACclk[5] = p);
160 	hw->MXoptionReg = mx;
168 	struct matrox_hw_state *hw = &minfo->hw;
172 	c2_ctl = hw->crtc2.ctl & ~0x4007;	/* Clear PLL + enable for CRTC2 */
174 	hw->DACreg[POS1064_XPWRCTRL] &= ~0x02;	/* Stop VIDEO PLL */
179 		hw->DACreg[POS1064_XPWRCTRL] &= ~0x10;	/* Powerdown CRTC2 */
193 		hw->DACreg[POS1064_XPWRCTRL] |= 0x02;
195 		outDAC1064(minfo, M1064_XPWRCTRL, hw->DACreg[POS1064_XPWRCTRL]);
199 	hw->DACreg[POS1064_XPIXCLKCTRL] &= ~M1064_XPIXCLKCTRL_PLL_UP;
201 		hw->DACreg[POS1064_XPIXCLKCTRL] |= M1064_XPIXCLKCTRL_PLL_UP;
203 		outDAC1064(minfo, M1064_XPIXCLKCTRL, hw->DACreg[POS1064_XPIXCLKCTRL]);
206 	if (c2_ctl != hw->crtc2.ctl) {
207 		hw->crtc2.ctl = c2_ctl;
217 			hw->DACreg[POS1064_XPANMODE] = 0x00;	/* 0-50 */
219 			hw->DACreg[POS1064_XPANMODE] = 0x08;	/* 34-62 */
221 			hw->DACreg[POS1064_XPANMODE] = 0x10;	/* 42-78 */
223 			hw->DACreg[POS1064_XPANMODE] = 0x18;	/* 62-92 */
225 			hw->DACreg[POS1064_XPANMODE] = 0x20;	/* 74-108 */
227 			hw->DACreg[POS1064_XPANMODE] = 0x28;	/* 94-122 */
229 			hw->DACreg[POS1064_XPANMODE] = 0x30;	/* 108-132 */
231 			hw->DACreg[POS1064_XPANMODE] = 0x38;	/* 120-168 */
236 			hw->DACreg[POS1064_XPANMODE] = 0x00;	/* 0-54 */
238 			hw->DACreg[POS1064_XPANMODE] = 0x08;	/* 38-70 */
240 			hw->DACreg[POS1064_XPANMODE] = 0x10;	/* 56-96 */
242 			hw->DACreg[POS1064_XPANMODE] = 0x18;	/* 80-114 */
244 			hw->DACreg[POS1064_XPANMODE] = 0x20;	/* 102-144 */
246 			hw->DACreg[POS1064_XPANMODE] = 0x28;	/* 132-166 */
248 			hw->DACreg[POS1064_XPANMODE] = 0x30;	/* 154-182 */
250 			hw->DACreg[POS1064_XPANMODE] = 0x38;	/* 170-204 */
258 	struct matrox_hw_state *hw = &minfo->hw;
260 	hw->DACreg[POS1064_XMISCCTRL] &= M1064_XMISCCTRL_DAC_WIDTHMASK;
261 	hw->DACreg[POS1064_XMISCCTRL] |= M1064_XMISCCTRL_LUT_EN;
262 	hw->DACreg[POS1064_XPIXCLKCTRL] = M1064_XPIXCLKCTRL_PLL_UP | M1064_XPIXCLKCTRL_EN | M1064_XPIXCLKCTRL_SRC_PLL;
265 		hw->DACreg[POS1064_XPWRCTRL] = 0x1F;	/* powerup everything */
266 		hw->DACreg[POS1064_XOUTPUTCONN] = 0x00;	/* disable outputs */
267 		hw->DACreg[POS1064_XMISCCTRL] |= M1064_XMISCCTRL_DAC_EN;
271 				hw->DACreg[POS1064_XOUTPUTCONN] |= 0x01;	/* enable output; CRTC1/2 selection is in CRTC2 ctl */
274 				hw->DACreg[POS1064_XMISCCTRL] &= ~M1064_XMISCCTRL_DAC_EN;
279 				hw->DACreg[POS1064_XOUTPUTCONN] |= 0x04;
283 					hw->DACreg[POS1064_XOUTPUTCONN] |= 0x08;
285 					hw->DACreg[POS1064_XOUTPUTCONN] |= 0x0C;
289 				hw->DACreg[POS1064_XPWRCTRL] &= ~0x01;		/* Poweroff DAC2 */
294 				hw->DACreg[POS1064_XOUTPUTCONN] |= 0x20;
297 				hw->DACreg[POS1064_XOUTPUTCONN] |= 0x40;
306 				hw->DACreg[POS1064_XPWRCTRL] &= ~0x04;		/* Poweroff TMDS */
316 			hw->DACreg[POS1064_XPIXCLKCTRL] = M1064_XPIXCLKCTRL_PLL_UP | M1064_XPIXCLKCTRL_EN | M1064_XPIXCLKCTRL_SRC_EXT;
317 			hw->DACreg[POS1064_XMISCCTRL] |= GX00_XMISCCTRL_MFC_MAFC | G400_XMISCCTRL_VDO_MAFC12;
319 			hw->DACreg[POS1064_XMISCCTRL] |= GX00_XMISCCTRL_MFC_MAFC | G400_XMISCCTRL_VDO_C2_MAFC12;
321 			hw->DACreg[POS1064_XMISCCTRL] |= GX00_XMISCCTRL_MFC_PANELLINK | G400_XMISCCTRL_VDO_MAFC12;
323 			hw->DACreg[POS1064_XMISCCTRL] |= GX00_XMISCCTRL_MFC_DIS;
326 			hw->DACreg[POS1064_XMISCCTRL] |= M1064_XMISCCTRL_DAC_EN;
332 	struct matrox_hw_state *hw = &minfo->hw;
334 	outDAC1064(minfo, M1064_XPIXCLKCTRL, hw->DACreg[POS1064_XPIXCLKCTRL]);
335 	outDAC1064(minfo, M1064_XMISCCTRL, hw->DACreg[POS1064_XMISCCTRL]);
341 			outDAC1064(minfo, M1064_XPWRCTRL, hw->DACreg[POS1064_XPWRCTRL]);
342 			outDAC1064(minfo, M1064_XPANMODE, hw->DACreg[POS1064_XPANMODE]);
343 			outDAC1064(minfo, M1064_XOUTPUTCONN, hw->DACreg[POS1064_XOUTPUTCONN]);
350 	struct matrox_hw_state *hw = &minfo->hw;
354 	memcpy(hw->DACreg, MGA1064_DAC, sizeof(MGA1064_DAC_regs));
358 			hw->DACreg[POS1064_XMULCTRL] = M1064_XMULCTRL_DEPTH_8BPP | M1064_XMULCTRL_GRAPHICS_PALETIZED;
362 				hw->DACreg[POS1064_XMULCTRL] = M1064_XMULCTRL_DEPTH_15BPP_1BPP | M1064_XMULCTRL_GRAPHICS_PALETIZED;
364 				hw->DACreg[POS1064_XMULCTRL] = M1064_XMULCTRL_DEPTH_16BPP | M1064_XMULCTRL_GRAPHICS_PALETIZED;
367 			hw->DACreg[POS1064_XMULCTRL] = M1064_XMULCTRL_DEPTH_24BPP | M1064_XMULCTRL_GRAPHICS_PALETIZED;
370 			hw->DACreg[POS1064_XMULCTRL] = M1064_XMULCTRL_DEPTH_32BPP | M1064_XMULCTRL_GRAPHICS_PALETIZED;
375 	hw->DACreg[POS1064_XVREFCTRL] = minfo->features.DAC1064.xvrefctrl;
376 	hw->DACreg[POS1064_XGENCTRL] &= ~M1064_XGENCTRL_SYNC_ON_GREEN_MASK;
377 	hw->DACreg[POS1064_XGENCTRL] |= (m->sync & FB_SYNC_ON_GREEN)?M1064_XGENCTRL_SYNC_ON_GREEN:M1064_XGENCTRL_NO_SYNC_ON_GREEN;
378 	hw->DACreg[POS1064_XCURADDL] = 0;
379 	hw->DACreg[POS1064_XCURADDH] = 0;
387 	struct matrox_hw_state *hw = &minfo->hw;
395 			hw->DACpal[i * 3 + 0] = i;
396 			hw->DACpal[i * 3 + 1] = i;
397 			hw->DACpal[i * 3 + 2] = i;
405 				hw->DACpal[i * 3 + 0] = i << 3;
406 				hw->DACpal[i * 3 + 1] = i << 3;
407 				hw->DACpal[i * 3 + 2] = i << 3;
409 				hw->DACpal[(i + 128) * 3 + 0] = i << 3;
410 				hw->DACpal[(i + 128) * 3 + 1] = i << 3;
411 				hw->DACpal[(i + 128) * 3 + 2] = i << 3;
417 				hw->DACpal[i * 3 + 0] = i << 3;
418 				hw->DACpal[i * 3 + 1] = i << 2;
419 				hw->DACpal[i * 3 + 2] = i << 3;
423 		memset(hw->DACpal, 0, 768);
430 	struct matrox_hw_state *hw = &minfo->hw;
438 	if ((inDAC1064(minfo, DAC1064_XSYSPLLM) != hw->DACclk[3]) ||
439 	    (inDAC1064(minfo, DAC1064_XSYSPLLN) != hw->DACclk[4]) ||
440 	    (inDAC1064(minfo, DAC1064_XSYSPLLP) != hw->DACclk[5])) {
441 		outDAC1064(minfo, DAC1064_XSYSPLLM, hw->DACclk[3]);
442 		outDAC1064(minfo, DAC1064_XSYSPLLN, hw->DACclk[4]);
443 		outDAC1064(minfo, DAC1064_XSYSPLLP, hw->DACclk[5]);
450 				outDAC1064(minfo, MGA1064_DAC_regs[i], hw->DACreg[i]);
470 		dprintk("R%02X=%02X ", MGA1064_DAC_regs[i], minfo->hw.DACreg[i]);
475 		dprintk("C%02X=%02X ", i, minfo->hw.DACclk[i]);
492 			outDAC1064(minfo, M1064_XPIXPLLCM + i, minfo->hw.DACclk[i]);
537 	struct matrox_hw_state *hw = &minfo->hw;
544 	hw->MiscOutReg = 0xCB;
546 		hw->MiscOutReg &= ~0x40;
548 		hw->MiscOutReg &= ~0x80;
550 		hw->CRTCEXT[3] |= 0x40;
560 	struct matrox_hw_state *hw = &minfo->hw;
565 	hw->MXoptionReg &= ~0x2000;
568 	hw->MiscOutReg = 0xEF;
570 		hw->MiscOutReg &= ~0x40;
572 		hw->MiscOutReg &= ~0x80;
574 		hw->CRTCEXT[3] |= 0x40;
673 	struct matrox_hw_state *hw = &minfo->hw;
688 	hw->MXoptionReg &= 0xC0000100;
689 	hw->MXoptionReg |= 0x00094E20;
691 		hw->MXoptionReg &= ~0x00000100;
693 		hw->MXoptionReg &= ~0x40000000;
695 		hw->MXoptionReg |=  0x20000000;
696 	pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);
719 	pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg | 4);
721 	pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg);
739 	pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg | 4);
741 	pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg);
748 	minfo->hw.MXoptionReg &= ~0x001F8000;
749 	pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg);
752 	minfo->hw.MXoptionReg &= ~0x00207E00;
753 	minfo->hw.MXoptionReg |= 0x00207E00 & minfo->values.reg.opt;
754 	pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg);
775 	minfo->hw.MXoptionReg |= 0x001F8000 & minfo->values.reg.opt;
776 	pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg);
794 	/* minfo->hw.MXoptionReg = minfo->values.reg.opt; */
795 	minfo->hw.MXoptionReg &= 0xC0000100;
796 	minfo->hw.MXoptionReg |= 0x00000020;
798 		minfo->hw.MXoptionReg &= ~0x00000100;
800 		minfo->hw.MXoptionReg &= ~0x40000000;
802 		minfo->hw.MXoptionReg |=  0x20000000;
803 	minfo->hw.MXoptionReg |= minfo->values.reg.opt & 0x03400040;
804 	pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg);
842 	struct matrox_hw_state *hw = &minfo->hw;
892 	hw->MXoptionReg &= 0xC0000100;
893 	hw->MXoptionReg |= 0x00000020;
895 		hw->MXoptionReg &= ~0x00000100;
897 		hw->MXoptionReg &= ~0x40000000;
899 		hw->MXoptionReg |=  0x20000000;
900 	pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);
908 		hw->MXoptionReg |= 0x1080;
909 		pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);
931 			hw->MXoptionReg &= ~0x1000;
934 		hw->MXoptionReg |= 0x00078020;
941 			hw->MXoptionReg |= minfo->values.reg.opt & 0x1C00;
943 			hw->MXoptionReg |= (minfo->devflags.memtype & 7) << 10;
945 			hw->MXoptionReg |= 0x4000;
953 		hw->MXoptionReg |= 0x00078020;
961 			hw->MXoptionReg |= minfo->values.reg.opt & 0x1C00;
963 			hw->MXoptionReg |= (minfo->devflags.memtype & 7) << 10;
965 			hw->MXoptionReg |= 0x4000;
973 		hw->MXoptionReg |= 0x00040020;
975 	pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);
982 	struct matrox_hw_state *hw = &minfo->hw;
1001 				hw->MXoptionReg |= 0x40;	/* FIXME... */
1002 				pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);
1009 		hw->DACclk[3] = inDAC1064(minfo, DAC1064_XSYSPLLM);
1010 		hw->DACclk[4] = inDAC1064(minfo, DAC1064_XSYSPLLN);
1011 		hw->DACclk[5] = inDAC1064(minfo, DAC1064_XSYSPLLP);
1040 	struct matrox_hw_state *hw = &minfo->hw;
1048 	pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);
1058 		mga_setr(M_EXTVGA_INDEX, i, hw->CRTCEXT[i]);
1067 	struct matrox_hw_state *hw = &minfo->hw;
1075 	pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);
1081 		mga_setr(M_EXTVGA_INDEX, 8, hw->CRTCEXT[8]);
1084 		mga_setr(M_EXTVGA_INDEX, i, hw->CRTCEXT[i]);