Cross Reference: /drivers/video/omap2/dss/dsi.c

Lines Matching refs:cinfo
1281 /* calculate clock rates using dividers in cinfo */
1283 		struct dsi_clock_info *cinfo)
1288 	if (cinfo->regn == 0 || cinfo->regn > dsi->regn_max)
1291 	if (cinfo->regm == 0 || cinfo->regm > dsi->regm_max)
1294 	if (cinfo->regm_dispc > dsi->regm_dispc_max)
1297 	if (cinfo->regm_dsi > dsi->regm_dsi_max)
1300 	if (cinfo->use_sys_clk) {
1301 		cinfo->clkin = clk_get_rate(dsi->sys_clk);
1304 		cinfo->highfreq = 0;
1306 		cinfo->clkin = dispc_mgr_pclk_rate(dssdev->manager->id);
1308 		if (cinfo->clkin < 32000000)
1309 			cinfo->highfreq = 0;
1311 			cinfo->highfreq = 1;
1314 	cinfo->fint = cinfo->clkin / (cinfo->regn * (cinfo->highfreq ? 2 : 1));
1316 	if (cinfo->fint > dsi->fint_max || cinfo->fint < dsi->fint_min)
1319 	cinfo->clkin4ddr = 2 * cinfo->regm * cinfo->fint;
1321 	if (cinfo->clkin4ddr > 1800 * 1000 * 1000)
1324 	if (cinfo->regm_dispc > 0)
1325 		cinfo->dsi_pll_hsdiv_dispc_clk =
1326 			cinfo->clkin4ddr / cinfo->regm_dispc;
1328 		cinfo->dsi_pll_hsdiv_dispc_clk = 0;
1330 	if (cinfo->regm_dsi > 0)
1331 		cinfo->dsi_pll_hsdiv_dsi_clk =
1332 			cinfo->clkin4ddr / cinfo->regm_dsi;
1334 		cinfo->dsi_pll_hsdiv_dsi_clk = 0;
1478 		struct dsi_clock_info *cinfo)
1489 	dsi->current_cinfo.use_sys_clk = cinfo->use_sys_clk;
1490 	dsi->current_cinfo.highfreq = cinfo->highfreq;
1492 	dsi->current_cinfo.fint = cinfo->fint;
1493 	dsi->current_cinfo.clkin4ddr = cinfo->clkin4ddr;
1495 			cinfo->dsi_pll_hsdiv_dispc_clk;
1497 			cinfo->dsi_pll_hsdiv_dsi_clk;
1499 	dsi->current_cinfo.regn = cinfo->regn;
1500 	dsi->current_cinfo.regm = cinfo->regm;
1501 	dsi->current_cinfo.regm_dispc = cinfo->regm_dispc;
1502 	dsi->current_cinfo.regm_dsi = cinfo->regm_dsi;
1504 	DSSDBG("DSI Fint %ld\n", cinfo->fint);
1507 			cinfo->use_sys_clk ? "dss_sys_clk" : "pclkfree",
1508 			cinfo->clkin,
1509 			cinfo->highfreq);
1513 			cinfo->regm,
1514 			cinfo->regn,
1515 			cinfo->clkin,
1516 			cinfo->highfreq + 1,
1517 			cinfo->clkin4ddr);
1520 			cinfo->clkin4ddr / 1000 / 1000 / 2);
1522 	DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4);
1524 	DSSDBG("regm_dispc = %d, %s (%s) = %lu\n", cinfo->regm_dispc,
1527 		cinfo->dsi_pll_hsdiv_dispc_clk);
1528 	DSSDBG("regm_dsi = %d, %s (%s) = %lu\n", cinfo->regm_dsi,
1531 		cinfo->dsi_pll_hsdiv_dsi_clk);
1546 	l = FLD_MOD(l, cinfo->regn - 1, regn_start, regn_end);
1548 	l = FLD_MOD(l, cinfo->regm, regm_start, regm_end);
1550 	l = FLD_MOD(l, cinfo->regm_dispc > 0 ? cinfo->regm_dispc - 1 : 0,
1553 	l = FLD_MOD(l, cinfo->regm_dsi > 0 ? cinfo->regm_dsi - 1 : 0,
1557 	BUG_ON(cinfo->fint < dsi->fint_min || cinfo->fint > dsi->fint_max);
1560 		f = cinfo->fint < 1000000 ? 0x3 :
1561 			cinfo->fint < 1250000 ? 0x4 :
1562 			cinfo->fint < 1500000 ? 0x5 :
1563 			cinfo->fint < 1750000 ? 0x6 :
1571 	l = FLD_MOD(l, cinfo->use_sys_clk ? 0 : 1,
1573 	l = FLD_MOD(l, cinfo->highfreq,
1717 	struct dsi_clock_info *cinfo = &dsi->current_cinfo;
1730 			cinfo->use_sys_clk ? "dss_sys_clk" : "pclkfree");
1732 	seq_printf(s,	"Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn);
1735 			cinfo->clkin4ddr, cinfo->regm);
1741 			cinfo->dsi_pll_hsdiv_dispc_clk,
1742 			cinfo->regm_dispc,
1750 			cinfo->dsi_pll_hsdiv_dsi_clk,
1751 			cinfo->regm_dsi,
1764 			cinfo->clkin4ddr / 4);
1768 	seq_printf(s,	"LP_CLK\t\t%lu\n", cinfo->lp_clk);
4285 	struct dsi_clock_info cinfo;
4289 	cinfo.use_sys_clk = true;
4290 	cinfo.regn  = dssdev->clocks.dsi.regn;
4291 	cinfo.regm  = dssdev->clocks.dsi.regm;
4292 	cinfo.regm_dispc = dssdev->clocks.dsi.regm_dispc;
4293 	cinfo.regm_dsi = dssdev->clocks.dsi.regm_dsi;
4294 	r = dsi_calc_clock_rates(dssdev, &cinfo);
4300 	r = dsi_pll_set_clock_div(dsidev, &cinfo);