Lines Matching refs:base

142  * @base: Registers base address
151 void __iomem *base;
171 #define MERAM_ICB_OFFSET(base, idx, off) ((base) + (off) + (idx) * 0x20)
173 static inline void meram_write_icb(void __iomem *base, unsigned int idx,
176 iowrite32(val, MERAM_ICB_OFFSET(base, idx, off));
179 static inline unsigned long meram_read_icb(void __iomem *base, unsigned int idx,
182 return ioread32(MERAM_ICB_OFFSET(base, idx, off));
185 static inline void meram_write_reg(void __iomem *base, unsigned int off,
188 iowrite32(val, base + off);
191 static inline unsigned long meram_read_reg(void __iomem *base, unsigned int off)
193 return ioread32(base + off);
320 meram_write_icb(priv->base, cache->planes[0].cache->index, target,
322 meram_write_icb(priv->base, cache->planes[0].marker->index, target,
326 meram_write_icb(priv->base, cache->planes[1].cache->index,
328 meram_write_icb(priv->base, cache->planes[1].marker->index,
396 meram_write_icb(priv->base, plane->cache->index, MExxBSIZE,
398 meram_write_icb(priv->base, plane->marker->index, MExxBSIZE,
401 meram_write_icb(priv->base, plane->cache->index, MExxMNCF, bnm);
402 meram_write_icb(priv->base, plane->marker->index, MExxMNCF, bnm);
404 meram_write_icb(priv->base, plane->cache->index, MExxSBSIZE, xpitch);
405 meram_write_icb(priv->base, plane->marker->index, MExxSBSIZE, xpitch);
417 meram_write_icb(priv->base, plane->cache->index, MExxCTL,
421 meram_write_icb(priv->base, plane->marker->index, MExxCTL,
434 meram_write_icb(priv->base, plane->cache->index, MExxCTL,
436 meram_write_icb(priv->base, plane->marker->index, MExxCTL,
549 priv->regs[i] = meram_read_reg(priv->base, common_regs[i]);
556 meram_read_icb(priv->base, i, icb_regs[j]);
576 meram_write_icb(priv->base, i, icb_regs[j],
581 meram_write_reg(priv->base, common_regs[i], priv->regs[i]);
645 priv->base = ioremap_nocache(regs->start, resource_size(regs));
646 if (!priv->base) {
668 meram_write_reg(priv->base, MEVCR1, MEVCR1_AMD1);
680 iounmap(priv->base);
703 iounmap(priv->base);