Cross Reference: /drivers/video/via/via

Lines Matching refs:clock
23  * clock and PLL management functions
274 	printk(KERN_INFO "Using undocumented set clock state.\n%s", via_slap);
279 	printk(KERN_INFO "Using undocumented set clock source.\n%s", via_slap);
292 void via_clock_init(struct via_clock *clock, int gfx_chip)
297 		clock->set_primary_clock_state = dummy_set_clock_state;
298 		clock->set_primary_clock_source = dummy_set_clock_source;
299 		clock->set_primary_pll_state = dummy_set_pll_state;
300 		clock->set_primary_pll = cle266_set_primary_pll;
302 		clock->set_secondary_clock_state = dummy_set_clock_state;
303 		clock->set_secondary_clock_source = dummy_set_clock_source;
304 		clock->set_secondary_pll_state = dummy_set_pll_state;
305 		clock->set_secondary_pll = cle266_set_secondary_pll;
307 		clock->set_engine_pll_state = dummy_set_pll_state;
308 		clock->set_engine_pll = dummy_set_pll;
319 		clock->set_primary_clock_state = set_primary_clock_state;
320 		clock->set_primary_clock_source = set_primary_clock_source;
321 		clock->set_primary_pll_state = set_primary_pll_state;
322 		clock->set_primary_pll = k800_set_primary_pll;
324 		clock->set_secondary_clock_state = set_secondary_clock_state;
325 		clock->set_secondary_clock_source = set_secondary_clock_source;
326 		clock->set_secondary_pll_state = set_secondary_pll_state;
327 		clock->set_secondary_pll = k800_set_secondary_pll;
329 		clock->set_engine_pll_state = set_engine_pll_state;
330 		clock->set_engine_pll = k800_set_engine_pll;
334 		clock->set_primary_clock_state = set_primary_clock_state;
335 		clock->set_primary_clock_source = set_primary_clock_source;
336 		clock->set_primary_pll_state = set_primary_pll_state;
337 		clock->set_primary_pll = vx855_set_primary_pll;
339 		clock->set_secondary_clock_state = set_secondary_clock_state;
340 		clock->set_secondary_clock_source = set_secondary_clock_source;
341 		clock->set_secondary_pll_state = set_secondary_pll_state;
342 		clock->set_secondary_pll = vx855_set_secondary_pll;
344 		clock->set_engine_pll_state = set_engine_pll_state;
345 		clock->set_engine_pll = vx855_set_engine_pll;