Searched defs:IER (Results 1 - 22 of 22) sorted by relevance

/drivers/macintosh/
H A Dvia-cuda.c50 #define IER (14*RS) /* Interrupt enable register */ macro
63 /* Bits in IFR and IER */
64 #define IER_SET 0x80 /* set bits in IER */
65 #define IER_CLR 0 /* clear bits in IER */
187 out_8(&via[IER], IER_SET|SR_INT); /* enable interrupt from SR */
269 out_8(&via[IER], 0x7f); /* disable interrupts from VIA */
270 (void)in_8(&via[IER]);
272 out_8(&via[IER], SR_INT); /* disable SR interrupt from VIA */
H A Dvia-macii.c56 #define IER (14*RS) /* Interrupt enable register */ macro
68 /* Bits in IFR and IER */
69 #define IER_SET 0x80 /* set bits in IER */
70 #define IER_CLR 0 /* clear bits in IER */
H A Dvia-maciisi.c40 #define IER (14*RS) /* Interrupt enable register */ macro
53 /* Bits in IFR and IER */
54 #define IER_SET 0x80 /* set bits in IER */
55 #define IER_CLR 0 /* clear bits in IER */
150 via[IER] = IER_CLR | SR_INT;
186 via[IER] = IER_SET | SR_INT;
205 via[IER] = IER_SET | SR_INT;
H A Dvia-pmu68k.c62 #define IER (14*RS) /* Interrupt enable register */ macro
74 /* Bits in IFR and IER */
H A Dvia-pmu.c94 #define IER (14*RS) /* Interrupt enable register */ macro
106 /* Bits in IFR and IER */
107 #define IER_SET 0x80 /* set bits in IER */
108 #define IER_CLR 0 /* clear bits in IER */
344 out_8(&via[IER], IER_CLR | 0x7f); /* disable all intrs */
433 out_8(&via[IER], IER_SET | SR_INT | CB1_INT);
1301 out_8(&via[IER], CB1_INT | IER_CLR);
1325 out_8(&via[IER], CB1_INT | IER_SET);
1572 intr, in_8(&via[IER]), pmu_state);
1777 out_8(&via[IER], IER_CL
[all...]
/drivers/net/hamradio/
H A Dbaycom_ser_fdx.c108 #define IER(iobase) (iobase+1) macro
447 outb(0, IER(dev->base_addr));
464 outb(0x0a, IER(dev->base_addr));
488 outb(0, IER(dev->base_addr));
H A Dbaycom_ser_hdx.c96 #define IER(iobase) (iobase+1) macro
492 outb(0, IER(dev->base_addr));
501 outb(2, IER(dev->base_addr));
524 outb(0, IER(dev->base_addr));
H A Dyam.c166 #define IER(iobase) (iobase+1) macro
308 outb(0, IER(iobase));
480 outb(0, IER(dev->base_addr));
495 outb(ENABLE_RTXINT, IER(dev->base_addr));
890 outb(0, IER(dev->base_addr));
933 outb(0, IER(dev->base_addr));
/drivers/spi/
H A Dspi-sh-msiof.c55 #define IER 0x44 macro
123 sh_msiof_write(p, IER, 0);
213 sh_msiof_write(p, IER, STR_TEOF | STR_REOF);
498 sh_msiof_write(p, IER, 0);
/drivers/tty/
H A Damiserial.c107 int IER; /* Interrupt Enable Register */ member in struct:serial_state
196 if (info->IER & UART_IER_THRI) {
197 info->IER &= ~UART_IER_THRI;
218 && !(info->IER & UART_IER_THRI)) {
219 info->IER |= UART_IER_THRI;
353 info->IER &= ~UART_IER_THRI;
375 info->IER &= ~UART_IER_THRI;
430 info->IER |= UART_IER_THRI;
445 info->IER &= ~UART_IER_THRI;
464 if(info->IER
[all...]
H A Dmxser.c239 int IER; /* Interrupt Enable Register */ member in struct:mxser_port
711 info->IER &= ~UART_IER_MSI;
715 info->IER |= UART_IER_MSI;
725 outb(info->IER & ~UART_IER_THRI,
728 info->IER |= UART_IER_THRI;
729 outb(info->IER, info->ioaddr +
739 info->IER &= ~UART_IER_THRI;
740 outb(info->IER, info->ioaddr +
754 info->IER |= UART_IER_MSI;
756 outb(info->IER, inf
[all...]
/drivers/usb/serial/
H A Dio_16654.h30 // the EdgePort firmware -- that includes THR, RHR, IER, FCR.
35 #define IER 1 // ! Interrupt Enable Register macro
H A Dmos7720.c133 IER, enumerator in enum:mos_regs
162 0x01, /* IER */
1057 * 1 : IER
1077 write_mos_reg(serial, port_number, IER, 0x00);
1093 write_mos_reg(serial, port_number, IER, 0x00);
1096 write_mos_reg(serial, port_number, IER, 0x0c);
1187 IER, 0x00);
1421 write_mos_reg(serial, port_number, IER, 0x00);
1675 write_mos_reg(serial, port_number, IER, 0x00);
1714 write_mos_reg(serial, port_number, IER,
[all...]
/drivers/net/irda/
H A Dnsc-ircc.h79 #define IER 0x01 /* Interrupt Enable Register*/ macro
/drivers/video/
H A Di740_reg.h229 #define IER 0x3030 macro
/drivers/video/i810/
H A Di810_regs.h44 #define IER 0x020A0 macro
/drivers/net/ethernet/natsemi/
H A Dns83820.c329 #define IER 0x18 macro
768 writel(1, dev->base + IER);
1388 writel(0, dev->base + IER);
1389 readl(dev->base + IER);
/drivers/video/intelfb/
H A Dintelfbhw.h92 #define IER 0x20A0 macro
/drivers/isdn/hisax/
H A Dhisax.h574 u_char IER; member in struct:elsa_hw
/drivers/net/wireless/
H A Dadm8211.h29 __le32 IER; /* 0x38 CSR7 */ member in struct:adm8211_csr
177 /* CSR7 - IER (Interrupt Enable Register) */
/drivers/gpu/drm/gma500/
H A Dpsb_intel_reg.h742 #define IER 0x020a0 macro
/drivers/gpu/drm/i915/
H A Di915_reg.h454 #define IER 0x020a0 macro

Completed in 357 milliseconds