Searched defs:RegAddr (Results 1 - 5 of 5) sorted by relevance

/drivers/staging/rtl8192e/rtl8192e/
H A Dr8192E_phy.c219 u32 RegAddr, u32 BitMask, u32 Data)
233 RegAddr);
238 phy_FwRFSerialWrite(dev, eRFPath, RegAddr, New_Value);
240 phy_FwRFSerialWrite(dev, eRFPath, RegAddr, Data);
246 RegAddr);
251 rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr,
254 rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, Data);
260 u32 RegAddr, u32 BitMask)
270 Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr);
274 RegAddr);
218 rtl8192_phy_SetRFReg(struct net_device *dev, enum rf90_radio_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data) argument
259 rtl8192_phy_QueryRFReg(struct net_device *dev, enum rf90_radio_path eRFPath, u32 RegAddr, u32 BitMask) argument
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/drivers/staging/rtl8192u/
H A Dr819xU_phy.c287 * u32 RegAddr //target addr to be modified
294 void rtl8192_phy_SetRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask, u32 Data) argument
307 Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr);
311 phy_FwRFSerialWrite(dev, eRFPath, RegAddr, New_Value);
313 phy_FwRFSerialWrite(dev, eRFPath, RegAddr, Data);
322 Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, RegAddr);
326 rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, New_Value);
328 rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, Data);
336 * u32 RegAddr //target addr to be readback
342 u32 rtl8192_phy_QueryRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u3 argument
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/drivers/media/common/tuners/
H A Dmxl5005s.c3597 u8 RegAddr[] = { local
3602 *count = ARRAY_SIZE(RegAddr);
3607 RegNum[i] = RegAddr[i];
3622 u8 RegAddr[] = {14, 15, 16, 17, 22, 43, 65, 68, 69, 70, 73, 92, 93, 106, local
3625 u8 RegAddr[] = {14, 15, 16, 17, 22, 43, 68, 69, 70, 73, 92, 93, 106, local
3628 u8 RegAddr[171];
3630 RegAddr[i] = i;
3634 *count = ARRAY_SIZE(RegAddr);
3637 RegNum[i] = RegAddr[i];
3650 u8 RegAddr[] local
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/drivers/tty/
H A Dsynclinkmp.c5538 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
5540 RegAddr += 256; /* port 0-1 SCA0, 2-3 SCA1 */ \
5543 RegAddr += 0x40; /* DMA access */ \
5545 RegAddr += 0x20; /* MSCI access */ \
5552 return *RegAddr;
5557 *RegAddr = Value;
5563 return *((u16 *)RegAddr);
5569 *((u16 *)RegAddr) = Value;
5574 unsigned char *RegAddr = (unsigned char *)info->statctrl_base; local
5575 return *RegAddr;
5580 unsigned char *RegAddr = (unsigned char *)info->statctrl_base; local
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H A Dsynclink.c4529 * RegAddr register address (number) for write
4537 static void usc_OutDmaReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue ) argument
4542 outw( RegAddr + info->mbre_bit, info->io_base );
4559 * RegAddr register address (number) to read from
4566 static u16 usc_InDmaReg( struct mgsl_struct *info, u16 RegAddr )
4571 outw( RegAddr + info->mbre_bit, info->io_base );
4585 * RegAddr register address (number) to write to
4593 static void usc_OutReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue ) argument
4595 outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
4612 * RegAddr registe
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