Searched defs:TxAvailable (Results 1 - 5 of 5) sorted by relevance

/drivers/net/ethernet/3com/
H A D3c589_cs.c98 TxAvailable = 0x0008, enumerator in enum:c509status
461 outw(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
463 outw(SetIntrEnb | IntLatch | TxAvailable | RxComplete | StatsFull
611 if (status & TxAvailable) {
614 outw(AckIntr | TxAvailable, ioaddr + EL3_CMD);
H A D3c509.c138 TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020, enumerator in enum:c509status
845 outw(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
921 if (status & TxAvailable) {
925 outw(AckIntr | TxAvailable, ioaddr + EL3_CMD);
1436 outw(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
1438 outw(SetIntrEnb | IntLatch|TxAvailable|TxComplete|RxComplete|StatsFull,
H A D3c515.c206 TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020, enumerator in enum:corkscrew_status
859 (vp->full_bus_master_tx ? DownComplete : TxAvailable) |
863 outw(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
865 outw(SetIntrEnb | IntLatch | TxAvailable | RxComplete | StatsFull
1165 if (status & TxAvailable) {
1169 outw(AckIntr | TxAvailable, ioaddr + EL3_CMD);
1228 outw(SetIntrEnb | TxAvailable |
H A D3c574_cs.c148 TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020, enumerator in enum:elxl_status
668 outw(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
670 outw(SetIntrEnb | IntLatch | TxAvailable | RxComplete | StatsFull
801 if (status & TxAvailable) {
804 outw(AckIntr | TxAvailable, ioaddr + EL3_CMD);
H A D3c59x.c466 TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020, enumerator in enum:vortex_status
1718 (vp->full_bus_master_tx ? DownComplete : TxAvailable) |
1721 vp->intr_enable = SetIntrEnb | IntLatch | TxAvailable |
1727 iowrite16(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
2275 if (status & TxAvailable) {
2279 iowrite16(AckIntr | TxAvailable, ioaddr + EL3_CMD);
2291 * insufficient FIFO room, the TxAvailable test will succeed and call

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