Searched defs:ctl_reg (Results 1 - 7 of 7) sorted by relevance

/drivers/misc/
H A Dphantom.c61 u32 ctl_reg; member in struct:phantom_device
120 r.value |= dev->ctl_reg & PHN_CTL_AMP;
121 dev->ctl_reg = r.value;
310 dev->ctl_reg ^= PHN_CTL_AMP;
311 iowrite32(dev->ctl_reg, dev->iaddr + PHN_CONTROL);
/drivers/gpu/drm/i915/
H A Dintel_lvds.c75 u32 ctl_reg, lvds_reg, stat_reg; local
78 ctl_reg = PCH_PP_CONTROL;
82 ctl_reg = PP_CONTROL;
105 I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON);
117 u32 ctl_reg, lvds_reg, stat_reg; local
120 ctl_reg = PCH_PP_CONTROL;
124 ctl_reg = PP_CONTROL;
131 I915_WRITE(ctl_reg, I915_READ(ctl_reg)
[all...]
/drivers/net/ethernet/
H A Ddnet.c184 u32 mode_reg, ctl_reg; local
191 ctl_reg = dnet_readw_mac(bp, DNET_INTERNAL_RXTX_CONTROL_REG);
196 ctl_reg &=
199 ctl_reg |=
244 dnet_writew_mac(bp, DNET_INTERNAL_RXTX_CONTROL_REG, ctl_reg);
/drivers/spi/
H A Dspi-bfin-sport.c102 u16 ctl_reg; member in struct:bfin_sport_spi_slave_data
259 bfin_write(&drv_data->regs->tcr1, chip->ctl_reg);
263 bfin_write(&drv_data->regs->rcr1, chip->ctl_reg & ~(ITCLK | ITFS));
526 drv_data->cur_chip->ctl_reg);
594 if (chip_info->ctl_reg || chip_info->enable_dma) {
596 dev_err(&spi->dev, "don't set ctl_reg/enable_dma fields");
616 chip->ctl_reg &= ~TCKFE;
618 chip->ctl_reg |= TCKFE;
621 chip->ctl_reg |= TLSBIT;
623 chip->ctl_reg
[all...]
H A Dspi-bfin5xx.c112 u16 ctl_reg; member in struct:bfin_spi_slave_data
213 bfin_write(&drv_data->regs->ctl, chip->ctl_reg);
925 drv_data->cur_chip->ctl_reg);
1015 /* Make sure people stop trying to set fields via ctl_reg
1021 if (chip_info->ctl_reg & ~bfin_ctl_reg) {
1022 dev_err(&spi->dev, "do not set bits in ctl_reg "
1028 chip->ctl_reg = chip_info->ctl_reg;
1034 chip->ctl_reg &= bfin_ctl_reg;
1049 chip->ctl_reg |
[all...]
/drivers/scsi/lpfc/
H A Dlpfc_debugfs.c2936 void __iomem *ctl_reg; local
2972 ctl_reg = phba->sli4_hba.conf_regs_memmap_p +
2976 ctl_reg = phba->sli4_hba.conf_regs_memmap_p +
2980 ctl_reg = phba->sli4_hba.conf_regs_memmap_p +
2984 ctl_reg = phba->sli4_hba.conf_regs_memmap_p +
2988 ctl_reg = phba->sli4_hba.conf_regs_memmap_p +
2992 ctl_reg = phba->sli4_hba.conf_regs_memmap_p +
3002 reg_val = readl(ctl_reg);
3006 reg_val = readl(ctl_reg);
3009 writel(reg_val, ctl_reg);
[all...]
/drivers/net/ethernet/chelsio/cxgb4/
H A Dt4_hw.c195 u32 ctl_reg = PF_REG(mbox, CIM_PF_MAILBOX_CTRL); local
207 v = MBOWNER_GET(t4_read_reg(adap, ctl_reg));
209 v = MBOWNER_GET(t4_read_reg(adap, ctl_reg));
217 t4_write_reg(adap, ctl_reg, MBMSGVALID | MBOWNER(MBOX_OWNER_FW));
218 t4_read_reg(adap, ctl_reg); /* flush write */
232 v = t4_read_reg(adap, ctl_reg);
235 t4_write_reg(adap, ctl_reg, 0);
248 t4_write_reg(adap, ctl_reg, 0);

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