Searched defs:enable_mask (Results 1 - 5 of 5) sorted by relevance
| /arch/arm/mach-lpc32xx/ |
| H A D | clock.h | 35 u32 enable_mask; member in struct:clk
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| /arch/arm/mach-omap2/ |
| H A D | display.c | 130 u32 enable_mask, enable_shift; local
135 enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
140 enable_mask = OMAP4_DSI2_LANEENABLE_MASK;
150 reg &= ~enable_mask;
153 reg |= (lanes << enable_shift) & enable_mask;
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| /arch/arm/mach-ep93xx/ |
| H A D | clock.c | 36 u32 enable_mask; member in struct:clk
57 .enable_mask = EP93XX_SYSCON_DEVCFG_U1EN,
64 .enable_mask = EP93XX_SYSCON_DEVCFG_U2EN,
71 .enable_mask = EP93XX_SYSCON_DEVCFG_U3EN,
92 .enable_mask = EP93XX_SYSCON_PWRCNT_USH_EN,
98 .enable_mask = EP93XX_SYSCON_KEYTCHCLKDIV_KEN,
113 .enable_mask = EP93XX_SYSCON_CLKDIV_ENABLE,
120 .enable_mask = EP93XX_SYSCON_CLKDIV_ENABLE,
128 .enable_mask = EP93XX_SYSCON_I2SCLKDIV_SENA,
136 .enable_mask
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| /arch/arm/plat-omap/include/plat/ |
| H A D | clock.h | 113 * @enable_mask: mask of the DPLL mode bitfield in @control_reg
120 * @modes: possible values of @enable_mask
151 u32 enable_mask; member in struct:dpll_data
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| /arch/x86/kernel/cpu/ |
| H A D | perf_event.h | 458 u64 enable_mask)
464 wrmsrl(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask);
457 __x86_pmu_enable_event(struct hw_perf_event *hwc, u64 enable_mask) argument
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