Searched defs:enable_reg (Results 1 - 7 of 7) sorted by relevance

/arch/arm/mach-lpc32xx/
H A Dclock.h34 void __iomem *enable_reg; member in struct:clk
/arch/arm/mach-mxs/include/mach/
H A Dclock.h37 void __iomem *enable_reg; member in struct:clk
/arch/arm/plat-mxc/include/mach/
H A Dclock.h39 void __iomem *enable_reg; member in struct:clk
/arch/arm/mach-pnx4008/
H A Dclock.h26 u32 enable_reg; member in struct:clk
/arch/arm/mach-ep93xx/
H A Dclock.c35 void __iomem *enable_reg; member in struct:clk
56 .enable_reg = EP93XX_SYSCON_DEVCFG,
63 .enable_reg = EP93XX_SYSCON_DEVCFG,
70 .enable_reg = EP93XX_SYSCON_DEVCFG,
91 .enable_reg = EP93XX_SYSCON_PWRCNT,
97 .enable_reg = EP93XX_SYSCON_KEYTCHCLKDIV,
112 .enable_reg = EP93XX_SYSCON_VIDCLKDIV,
119 .enable_reg = EP93XX_SYSCON_I2SCLKDIV,
127 .enable_reg = EP93XX_SYSCON_I2SCLKDIV,
135 .enable_reg
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/arch/arm/plat-omap/include/plat/
H A Dclock.h204 * @enable_reg: register to write to enable the clock (see @enable_bit)
209 * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
250 void __iomem *enable_reg; member in struct:clk
/arch/arm/plat-omap/
H A Ddma.c1943 u32 val, enable_reg; local
1952 enable_reg = p->dma_read(IRQENABLE_L0, 0);
1953 val &= enable_reg; /* Dispatch only relevant interrupts */

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