| /arch/arm/plat-samsung/include/plat/ |
| H A D | hwmon.h | 20 * @mult: Multiply the ADC value read by this.
24 * hwmon expects (mV) by result = (value_read * @mult) / @div.
28 unsigned int mult; member in struct:s3c_hwmon_chcfg
|
| /arch/mn10300/include/asm/ |
| H A D | div64.h | 79 unsigned __muldiv64u(unsigned val, unsigned mult, unsigned div) argument
83 asm("mulu %2,%0 \n" /* MDR:val = val*mult */
87 : "0"(val), "ir"(mult), "r"(div)
100 signed __muldiv64s(signed val, signed mult, signed div) argument
104 asm("mul %2,%0 \n" /* MDR:val = val*mult */
108 : "0"(val), "ir"(mult), "r"(div)
|
| /arch/x86/include/asm/ |
| H A D | vgtod.h | 14 u32 mult; member in struct:vsyscall_gtod_data::__anon3074
|
| /arch/arm/mach-omap2/ |
| H A D | clkt2xxx_dpllcore.c | 108 u32 cur_rate, low, mult, div, valid_rate, done_rate; local
114 mult = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
115 mult &= OMAP24XX_CORE_CLK_SRC_MASK;
117 if ((rate == (cur_rate / 2)) && (mult == 2)) {
119 } else if ((rate == (cur_rate * 2)) && (mult == 1)) {
126 if (mult == 1)
143 mult = ((rate / 2) / 1000000);
147 mult = (rate / 1000000);
151 tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask));
|
| /arch/arm/kernel/ |
| H A D | sched_clock.c | 22 u32 mult; member in struct:clock_data
32 .mult = NSEC_PER_SEC / HZ,
44 static inline u64 cyc_to_ns(u64 cyc, u32 mult, u32 shift) argument
46 return (cyc * mult) >> shift;
71 return epoch_ns + cyc_to_ns((cyc - epoch_cyc) & mask, cd.mult, cd.shift);
86 cd.mult, cd.shift);
125 /* calculate the mult/shift to convert counter ticks to ns. */
126 clocks_calc_mult_shift(&cd.mult, &cd.shift, rate, NSEC_PER_SEC, 0);
139 wrap = cyc_to_ns((1ULL << bits) - 1, cd.mult, cd.shift);
144 res = cyc_to_ns(1ULL, cd.mult, c
[all...] |
| /arch/mips/cavium-octeon/ |
| H A D | csrc-octeon.c | 87 u64 mult = clocksource_mips.mult; local
92 "dmultu\t%[cnt],%[mult]\n\t"
101 : [cnt] "r" (cnt), [mult] "r" (mult), [shift] "r" (shift)
|
| /arch/arm/mach-davinci/ |
| H A D | clock.c | 370 u32 ctrl, mult = 1, prediv = 1, postdiv = 1; local
380 mult = __raw_readl(pll->base + PLLM);
382 mult = 2 * (mult & PLLM_PLLM_MASK);
384 mult = (mult & PLLM_PLLM_MASK) + 1;
410 rate *= mult;
420 if (mult > 1)
421 pr_debug("* %d ", mult);
440 unsigned int mult, unsigne
439 davinci_set_pllrate(struct pll_data *pll, unsigned int prediv, unsigned int mult, unsigned int postdiv) argument
[all...] |
| H A D | tnetv107x.c | 650 unsigned long mult = 0, prediv = 1, postdiv = 1; local
675 mult = __raw_readl(&sspll_regs[pll]->mult_factor);
691 if (mult)
692 ret += ((unsigned long long)ref * mult) / 256;
|
| H A D | da850.c | 813 unsigned int mult; member in struct:da850_opp
822 .mult = 19,
831 .mult = 17,
840 .mult = 31,
849 .mult = 25,
858 .mult = 25,
867 .mult = 20,
991 unsigned int prediv, mult, postdiv; local
998 mult = opp->mult;
[all...] |
| /arch/c6x/platforms/ |
| H A D | pll.c | 271 u32 ctrl, mult = 0, prediv = 0, postdiv = 0; local
288 mult = pll_read(pll, PLLM);
289 mult = (mult & PLLM_PLLM_MASK) + 1;
309 if (mult)
310 rate *= mult;
317 prediv, mult, postdiv, rate / 1000000);
|
| /arch/sh/kernel/cpu/sh4a/ |
| H A D | clock-sh7722.c | 57 unsigned long mult; local
60 mult = __raw_readl(DLLFRQ);
62 mult = 0;
64 return clk->parent->rate * mult;
79 unsigned long mult = 1; local
83 mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1);
87 return (clk->parent->rate * mult) / div;
|
| H A D | clock-sh7723.c | 58 unsigned long mult; local
61 mult = __raw_readl(DLLFRQ);
63 mult = 0;
65 return clk->parent->rate * mult;
80 unsigned long mult = 1; local
84 mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1);
88 return (clk->parent->rate * mult) / div;
|
| H A D | clock-sh7724.c | 61 unsigned long mult = 0; local
65 mult = __raw_readl(FLLFRQ) & 0x3ff;
70 return (clk->parent->rate * mult) / div;
85 unsigned long mult = 1; local
88 mult = (((__raw_readl(FRQCRA) >> 24) & 0x3f) + 1) * 2;
90 return clk->parent->rate * mult;
|
| H A D | clock-sh7343.c | 54 unsigned long mult; local
57 mult = __raw_readl(DLLFRQ);
59 mult = 0;
61 return clk->parent->rate * mult;
76 unsigned long mult = 1; local
79 mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1);
81 return clk->parent->rate * mult;
|
| H A D | clock-sh7366.c | 54 unsigned long mult; local
57 mult = __raw_readl(DLLFRQ);
59 mult = 0;
61 return clk->parent->rate * mult;
76 unsigned long mult = 1; local
80 mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1);
84 return (clk->parent->rate * mult) / div;
|
| /arch/x86/kernel/ |
| H A D | vsyscall_64.c | 84 struct clocksource *clock, u32 mult)
94 vsyscall_gtod_data.clock.mult = mult;
83 update_vsyscall(struct timespec *wall_time, struct timespec *wtm, struct clocksource *clock, u32 mult) argument
|
| /arch/arm/mach-shmobile/ |
| H A D | clock-r8a7740.c | 151 unsigned long mult = 1; local
154 mult = ((__raw_readl(clk->enable_reg) >> 24) & 0x7f) + 1;
156 return clk->parent->rate * mult;
|
| H A D | clock-sh7367.c | 96 unsigned long mult = 1; local
99 mult = (((__raw_readl(RTFRQCR) >> 24) & 0x3f) + 1) * 2;
101 return clk->parent->rate * mult;
123 unsigned long mult = 1; local
126 mult = (((__raw_readl(PLLC2CR) >> 24) & 0x3f) + 1) * 2;
128 return clk->parent->rate * mult;
|
| H A D | clock-sh7377.c | 105 unsigned long mult = 1; local
108 mult = (((__raw_readl(RTFRQCR) >> 24) & 0x3f) + 1) * 2;
110 return clk->parent->rate * mult;
132 unsigned long mult = 1; local
135 mult = (((__raw_readl(PLLC2CR) >> 24) & 0x3f) + 1) * 2;
137 return clk->parent->rate * mult;
|
| H A D | clock-sh7372.c | 123 unsigned long mult = 1; local
126 mult = (((__raw_readl(clk->enable_reg) >> 24) & 0x3f) + 1) * 2;
128 return clk->parent->rate * mult;
187 unsigned long mult = 1; local
192 * If the PLL is off, mult == 1, clk->rate will be updated in
196 mult = (((__raw_readl(PLLC2CR) >> 24) & 0x3f) + 1) * 2;
198 return clk->parent->rate * mult;
|
| H A D | clock-sh73a0.c | 143 unsigned long mult = 1; local
146 mult = (((__raw_readl(clk->enable_reg) >> 24) & 0x3f) + 1);
152 mult *= 2;
156 return clk->parent->rate * mult;
|
| /arch/arm/plat-spear/ |
| H A D | clock.c | 301 u32 mult = clk->div_factor ? clk->div_factor : 1; local
302 ret = clk_set_rate(clk->pclk, mult * rate);
461 u32 mult; local
465 mult = clk->div_factor ? clk->div_factor : 1;
466 return clk_round_rate(clk->pclk, mult * drate) / mult;
|
| /arch/ia64/kernel/ |
| H A D | time.c | 458 struct clocksource *c, u32 mult)
464 fsyscall_gtod_data.clk_mult = mult;
457 update_vsyscall(struct timespec *wall, struct timespec *wtm, struct clocksource *c, u32 mult) argument
|
| /arch/powerpc/kernel/ |
| H A D | time.c | 706 struct clocksource *clock, u32 mult)
719 new_tb_to_xs = (u64) mult * (19342813113834067ULL >> clock->shift);
776 printk(KERN_INFO "clocksource: %s mult[%x] shift[%d] registered\n",
777 clock->name, clock->mult, clock->shift);
802 printk_once(KERN_DEBUG "clockevent: %s mult[%x] shift[%d] cpu[%d]\n",
803 dec->name, dec->mult, dec->shift, cpu);
705 update_vsyscall(struct timespec *wall_time, struct timespec *wtm, struct clocksource *clock, u32 mult) argument
|
| /arch/s390/kernel/ |
| H A D | time.c | 150 cd->mult = 16777;
213 .mult = 1000,
224 struct clocksource *clock, u32 mult)
237 vdso_data->ntp_mult = mult;
223 update_vsyscall(struct timespec *wall_time, struct timespec *wtm, struct clocksource *clock, u32 mult) argument
|