Searched defs:pll_m (Results 1 - 5 of 5) sorted by relevance

/drivers/media/dvb/frontends/
H A Dtda1002x.h49 u8 pll_m; /* defaults: 8 */ member in struct:tda10023_config
H A Dtda10048.h70 u8 pll_m; member in struct:tda10048_config
H A Dtda10023.c54 u8 pll_m; member in struct:tda10023_state
241 /* 012 */ 0x28, 0xff, (state->pll_m-1),
545 state->pll_m = state->config->pll_m;
551 state->pll_m = 8;
557 state->sysclk = (state->xtal * state->pll_m / \
563 dprintk("DVB: TDA10023 %s: xtal:%d pll_m:%d pll_p:%d pll_n:%d\n",
564 __func__, state->xtal, state->pll_m, state->pll_p,
/drivers/video/
H A Dgbefb.c439 timing->pll_m = 4;
470 int pll_m, pll_n, pll_p, error, best_m, best_n, best_p, best_error; local
481 * pll_m, pll_n, pll_p define the following frequencies
482 * fvco = pll_m * 20Mhz / pll_n
487 for (pll_m = 1; pll_m < 256; pll_m++)
490 (pll_n << pll_p) / pll_m;
498 pll_m / pll_n >
500 pll_m / pll_
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H A Dgxt4500.c147 int pll_m; /* ref clock divisor */ member in struct:gxt4500_par
255 par->pll_m = m;
271 return par->refclk_ps * par->pll_m * par->pll_pd1 * par->pll_pd2
400 writereg(par, PLL_M, mdivtab[par->pll_m - 1]);

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