Searched defs:rate (Results 1 - 25 of 139) sorted by relevance

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/arch/arm/mach-nomadik/
H A Dclock.h12 unsigned long rate; member in struct:clk
/arch/arm/plat-versatile/
H A Dsched-clock.c37 void __init versatile_sched_clock_init(void __iomem *reg, unsigned long rate) argument
40 setup_sched_clock(versatile_read_sched_clock, 32, rate);
H A Dclock.c34 return clk->rate;
38 long clk_round_rate(struct clk *clk, unsigned long rate) argument
42 ret = clk->ops->round(clk, rate);
47 int clk_set_rate(struct clk *clk, unsigned long rate) argument
51 ret = clk->ops->set(clk, rate);
56 long icst_clk_round(struct clk *clk, unsigned long rate) argument
59 vco = icst_hz_to_vco(clk->params, rate);
64 int icst_clk_set(struct clk *clk, unsigned long rate) argument
68 vco = icst_hz_to_vco(clk->params, rate);
69 clk->rate
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/arch/arm/mach-vexpress/include/mach/
H A Dclkdev.h8 unsigned long rate; member in struct:clk
/arch/mips/include/asm/mach-bcm63xx/
H A Dbcm63xx_clk.h6 unsigned int rate; member in struct:clk
/arch/powerpc/sysdev/qe_lib/
H A Dusb.c23 int qe_usb_clock_set(enum qe_clock clk, int rate) argument
46 qe_setbrg(clk, rate, 1);
/arch/arm/mach-integrator/include/mach/
H A Dclkdev.h8 unsigned long rate; member in struct:clk
/arch/arm/mach-omap1/
H A Dopp.h19 unsigned long rate; member in struct:mpu_rate
/arch/arm/mach-omap2/
H A Dclock2xxx.c44 u32 rate; local
49 rate = clk_get_rate(sclk);
50 clk_set_rate(vclk, rate);
54 * Switch the MPU rate if specified on cmdline. We cannot do this
H A Dclkt34xx_dpll3m2.c36 * CORE DPLL (DPLL3) M2 divider rate programming functions
45 * @rate: rounded target rate
47 * Program the DPLL M2 divider with the rounded target rate. Returns
50 int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) argument
60 if (!clk || !rate)
63 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
64 if (validrate != rate)
67 sdrcrate = sdrc_ick_p->rate;
68 if (rate > cl
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H A Dclock3xxx.c44 int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate) argument
52 pr_err("clock: DPLL4 cannot change rate due to "
57 return omap3_noncore_dpll_set_rate(clk, rate);
82 * Switch the MPU rate if specified on cmdline. We cannot do this
H A Ddpll44xx.c87 * omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit
88 * @clk: struct clk * of the DPLL to compute the rate for
90 * Compute the output rate for the OMAP4 DPLL represented by @clk.
92 * OMAP4 ABE DPLL. Returns the DPLL's output rate (before M-dividers)
98 unsigned long rate; local
106 rate = omap2_get_dpll_rate(clk);
111 rate *= OMAP4430_REGM4XEN_MULT;
113 return rate;
117 * omap4_dpll_regm4xen_round_rate - round DPLL rate, considering REGM4XEN bit
118 * @clk: struct clk * of the DPLL to round a rate fo
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/arch/arm/mach-realview/include/mach/
H A Dclkdev.h7 unsigned long rate; member in struct:clk
/arch/arm/mach-versatile/include/mach/
H A Dclkdev.h7 unsigned long rate; member in struct:clk
/arch/arm/mach-zynq/include/mach/
H A Dclkdev.h23 unsigned long rate; member in struct:clk
/arch/arm/mach-highbank/
H A Dclock.c23 unsigned long rate; member in struct:clk
36 return clk->rate;
39 long clk_round_rate(struct clk *clk, unsigned long rate) argument
41 return clk->rate;
44 int clk_set_rate(struct clk *clk, unsigned long rate) argument
49 static struct clk eclk = { .rate = 200000000 };
50 static struct clk pclk = { .rate = 150000000 };
/arch/arm/mach-lpc32xx/
H A Dclock.h25 u32 rate; member in struct:clk
/arch/arm/mach-mmp/
H A Dclock.c81 unsigned long rate; local
84 rate = clk->ops->getrate(clk);
86 rate = clk->rate;
88 return rate;
92 int clk_set_rate(struct clk *clk, unsigned long rate) argument
99 ret = clk->ops->setrate(clk, rate);
H A Dclock.h24 unsigned long rate; member in struct:clk
35 .rate = _rate, \
43 .rate = _rate, \
51 .rate = _rate, \
59 .rate = _rate, \
/arch/arm/mach-mxs/
H A Dclock.c123 /* Retrieve the *current* clock rate. If the clock itself
126 * a valid clock rate
140 /* Round the requested clock rate to the nearest supported
141 * rate that is less than or equal to the requested rate.
144 long clk_round_rate(struct clk *clk, unsigned long rate) argument
149 return clk->round_rate(clk, rate);
153 /* Set the clock to the requested clock rate. The rate must
154 * match a supported rate exactl
156 clk_set_rate(struct clk *clk, unsigned long rate) argument
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/arch/arm/mach-pxa/
H A Dclock.c46 unsigned long rate; local
48 rate = clk->rate;
50 rate = clk->ops->getrate(clk);
52 return rate;
56 int clk_set_rate(struct clk *clk, unsigned long rate) argument
63 ret = clk->ops->setrate(clk, rate);
H A Dclock.h13 unsigned long rate; member in struct:clk
41 .rate = _rate, \
48 .rate = _rate, \
64 .rate = _rate, \
/arch/powerpc/kernel/
H A Dclock.c52 long clk_round_rate(struct clk *clk, unsigned long rate) argument
55 return clk_functions.clk_round_rate(clk, rate);
60 int clk_set_rate(struct clk *clk, unsigned long rate) argument
63 return clk_functions.clk_set_rate(clk, rate);
/arch/arm/mach-msm/
H A Dclock-pcom.c57 int pc_clk_set_rate(unsigned id, unsigned rate) argument
59 /* The rate _might_ be rounded off to the nearest KHz value by the
61 * that the exact rate was set successfully.
63 int rc = msm_proc_comm(PCOM_CLKCTL_RPC_SET_RATE, &id, &rate);
70 int pc_clk_set_min_rate(unsigned id, unsigned rate) argument
72 int rc = msm_proc_comm(PCOM_CLKCTL_RPC_MIN_RATE, &id, &rate);
79 int pc_clk_set_max_rate(unsigned id, unsigned rate) argument
81 int rc = msm_proc_comm(PCOM_CLKCTL_RPC_MAX_RATE, &id, &rate);
113 long pc_clk_round_rate(unsigned id, unsigned rate) argument
117 return rate;
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/arch/arm/mach-netx/
H A Dfb.c76 int clk_set_rate(struct clk *clk, unsigned long rate) argument

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