Searched defs:val (Results 176 - 200 of 819) sorted by relevance

1234567891011>>

/arch/arm/mach-ixp2000/include/mach/
H A Dplatform.h23 static inline void ixp2000_reg_write(volatile void *reg, unsigned long val) argument
25 *((volatile unsigned long *)reg) = val;
43 static inline void ixp2000_reg_wrb(volatile void *reg, unsigned long val) argument
47 *((volatile unsigned long *)reg) = val;
/arch/arm/mach-mmp/
H A Dpxa168.c136 uint32_t val; local
140 val = __raw_readl(APMU_WAKE_CLR);
141 __raw_writel(val | mask, APMU_WAKE_CLR);
/arch/arm/mach-msm/
H A Dsirc.c93 unsigned int val; local
96 val = readl(sirc_regs.int_polarity);
99 val |= mask;
101 val &= ~mask;
103 writel(val, sirc_regs.int_polarity);
105 val = readl(sirc_regs.int_type);
107 val |= mask;
110 val &= ~mask;
114 writel(val, sirc_regs.int_type);
H A Dvreg.c144 static int vreg_debug_set(void *data, u64 val) argument
147 switch (val) {
155 vreg_set_level(vreg, val);
161 static int vreg_debug_get(void *data, u64 *val) argument
166 *val = 0;
168 *val = 1;
173 static int vreg_debug_count_set(void *data, u64 val) argument
176 if (val > UINT_MAX)
177 val = UINT_MAX;
178 vreg->refcnt = val;
182 vreg_debug_count_get(void *data, u64 *val) argument
[all...]
/arch/arm/mach-netx/
H A Dgeneric.c93 unsigned int val, irq; local
95 val = readl(NETX_DPMAS_IF_CONF1);
101 val |= (1 << 26) << irq;
105 val &= ~((1 << 26) << irq);
109 val &= ~((1 << 26) << irq);
113 val |= (1 << 26) << irq;
116 writel(val, NETX_DPMAS_IF_CONF1);
124 unsigned int val, irq; local
129 val = readl(NETX_DPMAS_INT_EN);
130 val
139 unsigned int val, irq; local
151 unsigned int val, irq; local
[all...]
/arch/arm/mach-omap1/
H A Dtimer32k.c89 static inline void omap_32k_timer_write(int val, int reg) argument
91 omap_writew(val, OMAP1_32K_TIMER_BASE + reg);
/arch/arm/mach-omap2/
H A Domap4-common.c123 static void omap4_l2x0_set_debug(unsigned long val) argument
126 omap_smc1(0x100, val);
H A Dprminst44xx.c47 void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx) argument
52 __raw_writel(val, OMAP2_L4_IO_ADDRESS(_prm_bases[part] + inst + idx));
H A Dsdrc.c164 void omap2_sms_write_rot_control(u32 val, unsigned ctx) argument
166 sms_write_reg(val, SMS_ROT_CONTROL(ctx));
169 void omap2_sms_write_rot_size(u32 val, unsigned ctx) argument
171 sms_write_reg(val, SMS_ROT_SIZE(ctx));
174 void omap2_sms_write_rot_physical_ba(u32 val, unsigned ctx) argument
176 sms_write_reg(val, SMS_ROT_PHYSICAL_BA(ctx));
H A Dvp.c41 u32 val, sys_clk_rate, timeout, waittime; local
73 val = (voltdm->pmic->vp_erroroffset <<
76 voltdm->write(val, vp->vpconfig);
79 val = (waittime << vp->common->vstepmin_smpswaittimemin_shift) |
81 voltdm->write(val, vp->vstepmin);
84 val = (vstepmax << vp->common->vstepmax_stepmax_shift) |
86 voltdm->write(val, vp->vstepmax);
89 val = (vddmax << vp->common->vlimitto_vddmax_shift) |
92 voltdm->write(val, vp->vlimitto);
/arch/arm/mach-orion5x/
H A Drd88f5182-setup.c94 int val; local
97 val = 1;
99 val = 0;
103 gpio_set_value(RD88F5182_GPIO_DBG_LED, val);
/arch/arm/mach-w90x900/
H A Dcpu.c127 unsigned int pllclk, ahbclk, apbclk, val; local
167 val = __raw_readl(REG_CLKDIV);
168 val &= ~(0x03 << 24 | 0x03 << 26);
169 val |= (ahbclk << 24 | apbclk << 26);
170 __raw_writel(val, REG_CLKDIV);
176 unsigned long cpufreq, val; local
189 val = __raw_readl(REG_CKSKEW);
190 val &= ~0xff;
191 val |= DEFAULTSKEW;
192 __raw_writel(val, REG_CKSKE
[all...]
H A Dgpio.c66 static void nuc900_gpio_set(struct gpio_chip *chip, unsigned offset, int val) argument
77 if (val)
105 static int nuc900_dir_output(struct gpio_chip *chip, unsigned offset, int val) argument
121 if (val)
H A Dtime.c54 unsigned int val; local
56 val = __raw_readl(REG_TCSR0);
57 val &= ~(0x03 << 27);
62 val |= (PERIOD | COUNTEN | INTEN | PRESCALE);
66 val |= (ONESHOT | COUNTEN | INTEN | PRESCALE);
75 __raw_writel(val, REG_TCSR0);
81 unsigned int val; local
85 val = __raw_readl(REG_TCSR0);
86 val |= (COUNTEN | INTEN | PRESCALE);
87 __raw_writel(val, REG_TCSR
149 unsigned int val; local
[all...]
/arch/arm/plat-mxc/
H A Dulpi.c87 static int ulpi_write(struct usb_phy *otg, u32 val, u32 reg) argument
103 ((val & ULPIVW_WDATA_MASK) << ULPIVW_WDATA_SHIFT)), view);
/arch/arm/plat-samsung/include/plat/
H A Dpm.h70 * @val: Holder for the value saved from reg.
77 unsigned long val; member in struct:sleep_save
H A Duncompress.h45 uart_wr(unsigned int reg, unsigned int val) argument
50 *ptr = val;
/arch/arm/plat-samsung/
H A Dpm-check.c73 static u32 *s3c_pm_countram(struct resource *res, u32 *val) argument
83 *val += size * sizeof(u32);
84 return val;
108 static u32 *s3c_pm_makecheck(struct resource *res, u32 *val) argument
119 *val = crc32_le(~0, phys_to_virt(addr), left);
120 val++;
123 return val;
165 static u32 *s3c_pm_runcheck(struct resource *res, u32 *val) argument
197 if (calc != *val) {
199 "%08lx (%08x vs %08x)\n", addr, calc, *val);
[all...]
/arch/c6x/include/asm/
H A Dunaligned.h34 static inline void put_unaligned_le16(u16 val, void *p) argument
37 _p[0] = val;
38 _p[1] = val >> 8;
41 static inline void put_unaligned_be16(u16 val, void *p) argument
44 _p[0] = val >> 8;
45 _p[1] = val;
50 u32 val = (u32) p; local
53 : "+a"(val));
54 return val;
57 static inline void put_unaligned32(u32 val, voi argument
65 u64 val; local
72 put_unaligned64(u64 val, const void *p) argument
[all...]
/arch/c6x/platforms/
H A Demif.c49 u32 val; local
61 err = of_property_read_u32_array(node, "ti,dscr-dev-enable", &val, 1);
63 dscr_set_devstate(val, DSCR_DEVSTATE_ENABLED);
75 err = of_property_read_u32_array(node, "ti,emifa-burst-priority", &val, 1);
77 soc_writel(val, &regs->bprio);
79 err = of_property_read_u32_array(node, "ti,emifa-async-wait-control", &val, 1);
81 soc_writel(val, &regs->awcc);
H A Dplldata.c362 u32 val; local
372 err = of_property_read_u32(node, "clock-frequency", &val);
373 if (err || val == 0) {
375 node->full_name, (int)val / 1000000);
376 val = 25000000;
378 clkin1.rate = val;
380 err = of_property_read_u32(node, "ti,c64x+pll-bypass-delay", &val);
382 val = 5000;
383 pll->bypass_delay = val;
385 err = of_property_read_u32(node, "ti,c64x+pll-reset-delay", &val);
[all...]
/arch/cris/arch-v32/kernel/
H A Ddebugport.c183 putDebugChar(int val) argument
189 REG_WR_INT(ser, kgdb_port->instance, rw_dout, val);
/arch/cris/arch-v32/mach-a3/
H A Dcpufreq.c10 cris_sdram_freq_notifier(struct notifier_block *nb, unsigned long val,
134 cris_sdram_freq_notifier(struct notifier_block *nb, unsigned long val, argument
139 if (val == CPUFREQ_PRECHANGE) {
/arch/cris/arch-v32/mach-fs/
H A Dcpufreq.c10 cris_sdram_freq_notifier(struct notifier_block *nb, unsigned long val,
128 cris_sdram_freq_notifier(struct notifier_block *nb, unsigned long val, argument
133 if (val == CPUFREQ_PRECHANGE) {
/arch/frv/mm/
H A Dfault.c235 unsigned long dampr, damlr, val; local
243 val = pte_val(*pte);
247 printk(KERN_ALERT " PTE : %8p { %08lx }\n", pte, val);

Completed in 528 milliseconds

1234567891011>>