Searched defs:writereg (Results 1 - 21 of 21) sorted by relevance

/drivers/isdn/hisax/
H A Dasuscom.c62 writereg(unsigned int ale, unsigned int adr, u_char off, u_char data) function
86 writereg(cs->hw.asus.adr, cs->hw.asus.isac, offset, value);
110 writereg(cs->hw.asus.adr, cs->hw.asus.isac, offset | 0x80, value);
135 writereg(cs->hw.asus.adr,
145 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.asus.adr, \
184 writereg(cs->hw.asus.adr, cs->hw.asus.hscx, HSCX_MASK, 0xFF);
185 writereg(cs->hw.asus.adr, cs->hw.asus.hscx, HSCX_MASK + 0x40, 0xFF);
186 writereg(cs->hw.asus.adr, cs->hw.asus.isac, ISAC_MASK, 0xFF);
187 writereg(cs->hw.asus.adr, cs->hw.asus.isac, ISAC_MASK, 0x0);
188 writereg(c
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H A Davm_a1.c35 writereg(unsigned int adr, u_char off, u_char data) function
64 writereg(cs->hw.avm.isac, offset, value);
88 writereg(cs->hw.avm.hscx[hscx], offset, value);
96 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.avm.hscx[nr], reg, data)
127 writereg(cs->hw.avm.hscx[0], HSCX_MASK, 0xFF);
128 writereg(cs->hw.avm.hscx[1], HSCX_MASK, 0xFF);
129 writereg(cs->hw.avm.isac, ISAC_MASK, 0xFF);
130 writereg(cs->hw.avm.isac, ISAC_MASK, 0x0);
131 writereg(cs->hw.avm.hscx[0], HSCX_MASK, 0x0);
132 writereg(c
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H A Dbkm_a4t.c51 writereg(unsigned int ale, unsigned long adr, u_char off, u_char data) function
67 writereg(ale, adr, off, *data++);
82 writereg(cs->hw.ax.isac_ale, cs->hw.ax.isac_adr, offset, value);
106 writereg(cs->hw.ax.jade_ale, cs->hw.ax.jade_adr, offset + (jade == -1 ? 0 : (jade ? 0xC0 : 0x80)), value);
115 #define WRITEJADE(cs, nr, reg, data) writereg(cs->hw.ax.jade_ale, \
H A Dbkm_a8.c60 writereg(unsigned int ale, unsigned int adr, u_char off, u_char data) function
86 writereg(cs->hw.ax.base, cs->hw.ax.data_adr, offset | 0x80, value);
111 writereg(cs->hw.ax.base, cs->hw.ax.data_adr, offset + (hscx ? 0x40 : 0), value);
119 writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK,
129 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.ax.base, \
184 writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK, 0xFF);
185 writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK, 0xC0);
382 writereg(pci_ioaddr5, pci_ioaddr5 + 4,
384 writereg(pci_ioaddr4 + 0x08, pci_ioaddr4 + 0x0c,
386 writereg(pci_ioaddr
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H A Dix1_micro.c60 writereg(unsigned int ale, unsigned int adr, u_char off, u_char data) function
84 writereg(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, offset, value);
109 writereg(cs->hw.ix1.hscx_ale,
115 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.ix1.hscx_ale, \
154 writereg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_MASK, 0xFF);
155 writereg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_MASK + 0x40, 0xFF);
156 writereg(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, ISAC_MASK, 0xFF);
157 writereg(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, ISAC_MASK, 0);
158 writereg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_MASK, 0);
159 writereg(c
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H A Dmic.c50 writereg(unsigned int ale, unsigned int adr, u_char off, u_char data) function
74 writereg(cs->hw.mic.adr, cs->hw.mic.isac, offset, value);
99 writereg(cs->hw.mic.adr,
109 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.mic.adr, \
148 writereg(cs->hw.mic.adr, cs->hw.mic.hscx, HSCX_MASK, 0xFF);
149 writereg(cs->hw.mic.adr, cs->hw.mic.hscx, HSCX_MASK + 0x40, 0xFF);
150 writereg(cs->hw.mic.adr, cs->hw.mic.isac, ISAC_MASK, 0xFF);
151 writereg(cs->hw.mic.adr, cs->hw.mic.isac, ISAC_MASK, 0x0);
152 writereg(cs->hw.mic.adr, cs->hw.mic.hscx, HSCX_MASK, 0x0);
153 writereg(c
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H A Dniccy.c62 static inline void writereg(unsigned int ale, unsigned int adr, u_char off, function
85 writereg(cs->hw.niccy.isac_ale, cs->hw.niccy.isac, offset, value);
107 writereg(cs->hw.niccy.hscx_ale,
113 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.niccy.hscx_ale, \
162 writereg(cs->hw.niccy.hscx_ale, cs->hw.niccy.hscx, HSCX_MASK, 0xFF);
163 writereg(cs->hw.niccy.hscx_ale, cs->hw.niccy.hscx, HSCX_MASK + 0x40,
165 writereg(cs->hw.niccy.isac_ale, cs->hw.niccy.isac, ISAC_MASK, 0xFF);
166 writereg(cs->hw.niccy.isac_ale, cs->hw.niccy.isac, ISAC_MASK, 0);
167 writereg(cs->hw.niccy.hscx_ale, cs->hw.niccy.hscx, HSCX_MASK, 0);
168 writereg(c
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H A Ds0box.c22 writereg(unsigned int padr, signed int addr, u_char off, u_char val) { function
104 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.isac, offset, value);
128 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[hscx], offset, value);
136 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[nr], reg, data)
175 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[0], HSCX_MASK, 0xFF);
176 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[1], HSCX_MASK, 0xFF);
177 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.isac, ISAC_MASK, 0xFF);
178 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.isac, ISAC_MASK, 0x0);
179 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[0], HSCX_MASK, 0x0);
180 writereg(c
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H A Dsaphir.c52 writereg(unsigned int ale, unsigned int adr, u_char off, u_char data) function
76 writereg(cs->hw.saphir.ale, cs->hw.saphir.isac, offset, value);
101 writereg(cs->hw.saphir.ale, cs->hw.saphir.hscx,
107 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.saphir.ale, \
151 writereg(cs->hw.saphir.ale, cs->hw.saphir.hscx, HSCX_MASK, 0xFF);
152 writereg(cs->hw.saphir.ale, cs->hw.saphir.hscx, HSCX_MASK + 0x40, 0xFF);
153 writereg(cs->hw.saphir.ale, cs->hw.saphir.isac, ISAC_MASK, 0xFF);
154 writereg(cs->hw.saphir.ale, cs->hw.saphir.isac, ISAC_MASK, 0);
155 writereg(cs->hw.saphir.ale, cs->hw.saphir.hscx, HSCX_MASK, 0);
156 writereg(c
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H A Dteleint.c64 writereg(unsigned int ale, unsigned int adr, u_char off, u_char data) function
113 writereg(cs->hw.hfc.addr | 1, cs->hw.hfc.addr, offset, value);
175 writereg(cs->hw.hfc.addr | 1, cs->hw.hfc.addr, ISAC_MASK, 0xFF);
176 writereg(cs->hw.hfc.addr | 1, cs->hw.hfc.addr, ISAC_MASK, 0x0);
H A Dteles3.c35 writereg(unsigned int adr, u_char off, u_char data) function
64 writereg(cs->hw.teles3.isac, offset, value);
88 writereg(cs->hw.teles3.hscx[hscx], offset, value);
96 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.teles3.hscx[nr], reg, data)
135 writereg(cs->hw.teles3.hscx[0], HSCX_MASK, 0xFF);
136 writereg(cs->hw.teles3.hscx[1], HSCX_MASK, 0xFF);
137 writereg(cs->hw.teles3.isac, ISAC_MASK, 0xFF);
138 writereg(cs->hw.teles3.isac, ISAC_MASK, 0x0);
139 writereg(cs->hw.teles3.hscx[0], HSCX_MASK, 0x0);
140 writereg(c
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H A Dgazel.c51 writereg(unsigned int adr, u_short off, u_char data) function
129 writereg(cs->hw.gazel.isac, off2, value);
224 writereg(cs->hw.gazel.hscx[hscx], off2, value);
354 writereg(addr, 0, 0);
356 writereg(addr, 0, 1);
H A Dsedlbauer.c138 writereg(unsigned int ale, unsigned int adr, u_char off, u_char data) function
162 writereg(cs->hw.sedl.adr, cs->hw.sedl.isac, offset, value);
186 writereg(cs->hw.sedl.adr, cs->hw.sedl.isac, offset | 0x80, value);
211 writereg(cs->hw.sedl.adr,
235 writereg(cs->hw.sedl.adr, cs->hw.sedl.hscx, offset, value);
249 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.sedl.adr, \
296 writereg(cs->hw.sedl.adr, cs->hw.sedl.hscx, HSCX_MASK, 0xFF);
297 writereg(cs->hw.sedl.adr, cs->hw.sedl.hscx, HSCX_MASK + 0x40, 0xFF);
298 writereg(cs->hw.sedl.adr, cs->hw.sedl.isac, ISAC_MASK, 0xFF);
299 writereg(c
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H A Ddiva.c100 writereg(unsigned int ale, unsigned int adr, u_char off, u_char data) function
140 writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, offset, value);
164 writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, offset | 0x80, value);
189 writereg(cs->hw.diva.hscx_adr,
278 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.diva.hscx_adr, \
309 writereg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_MASK, 0xFF);
310 writereg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_MASK + 0x40, 0xFF);
311 writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, ISAC_MASK, 0xFF);
312 writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, ISAC_MASK, 0x0);
313 writereg(c
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H A Delsa.c160 writereg(unsigned int ale, unsigned int adr, u_char off, u_char data) function
184 writereg(cs->hw.elsa.ale, cs->hw.elsa.isac, offset, value);
208 writereg(cs->hw.elsa.ale, cs->hw.elsa.isac, offset | 0x80, value);
233 writereg(cs->hw.elsa.ale,
272 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.elsa.ale, \
333 writereg(cs->hw.elsa.ale, cs->hw.elsa.hscx, HSCX_MASK, 0xFF);
334 writereg(cs->hw.elsa.ale, cs->hw.elsa.hscx, HSCX_MASK + 0x40, 0xFF);
335 writereg(cs->hw.elsa.ale, cs->hw.elsa.isac, ISAC_MASK, 0xFF);
355 writereg(cs->hw.elsa.ale, cs->hw.elsa.hscx, HSCX_MASK, 0x0);
356 writereg(c
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/drivers/net/ethernet/cirrus/
H A Dmac89x0.c162 writereg(struct net_device *dev, int portno, int value) function
309 writereg(dev, PP_SelfCTL, readreg(dev, PP_SelfCTL) | POWER_ON_RESET);
335 writereg(dev, PP_BusCTL, readreg(dev, PP_BusCTL) & ~ENABLE_IRQ);
343 writereg(dev, PP_CS8900_ISAINT, 0);
345 writereg(dev, PP_CS8920_ISAINT, 0);
349 writereg(dev, PP_IA+i*2, dev->dev_addr[i*2] | (dev->dev_addr[i*2+1] << 8));
352 writereg(dev, PP_LineCTL, readreg(dev, PP_LineCTL) | SERIAL_RX_ON | SERIAL_TX_ON);
356 writereg(dev, PP_RxCTL, DEF_RX_ACCEPT);
360 writereg(dev, PP_RxCFG, lp->curr_rx_cfg);
362 writereg(de
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H A Dcs89x0.c422 writereg(struct net_device *dev, u16 regno, u16 value) function
450 writereg(dev, PP_EECMD, (off + i) | EEPROM_READ_CMD);
837 writereg(dev, PP_CS8900_ISADMA, dma-5);
839 writereg(dev, PP_CS8920_ISADMA, dma);
963 writereg(dev, PP_SelfCTL, readreg(dev, PP_SelfCTL) | POWER_ON_RESET);
1004 writereg(dev, PP_SelfCTL, selfcontrol);
1031 writereg(dev, PP_LineCTL, lp->linectl &~ AUI_ONLY);
1055 writereg(dev, PP_TestCTL, readreg(dev, PP_TestCTL) | FDX_8900);
1072 writereg(dev, PP_AutoNegCTL, lp->auto_neg_cnf & AUTO_NEG_MASK);
1101 writereg(de
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/drivers/media/video/zoran/
H A Dvideocodec.h83 writereg -> ref. to write-fn to register (setup by master, used by slave)
331 void (*writereg) (struct videocodec * codec,
327 void (*writereg) (struct videocodec * codec, member in struct:videocodec_master
/drivers/net/ethernet/amd/
H A Dni65.c159 #define writereg(val,reg) {outw(reg,PORT+L_ADDRREG);inw(PORT+L_ADDRREG); \
166 #define writedatareg(val) { writereg(val,CSR0); }
169 #define writereg(val,reg) {outw(reg,PORT+L_ADDRREG);outw(val,PORT+L_DATAREG);} macro
171 #define writedatareg(val) { writereg(val,CSR0); }
273 writereg(CSR0_STOP | CSR0_CLRALL,CSR0); /* STOP */
282 writereg( (csr80 & 0x3fff) ,80); /* FIFO watermarks */
538 writereg(CSR0_INIT|CSR0_INEA,CSR0); /* trigger interrupt */
577 writereg(CSR0_CLRALL|CSR0_STOP,CSR0);
588 writereg(0,CSR3); /* busmaster/no word-swap */
590 writereg(pi
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H A Ddeclance.c294 static inline void writereg(volatile unsigned short *regptr, short value) function
311 writereg(&ll->rap, LE_CSR1);
312 writereg(&ll->rdp, (leptr & 0xFFFF));
313 writereg(&ll->rap, LE_CSR2);
314 writereg(&ll->rdp, leptr >> 16);
315 writereg(&ll->rap, LE_CSR3);
316 writereg(&ll->rdp, lp->busmaster_regval);
319 writereg(&ll->rap, LE_CSR0);
530 writereg(&ll->rap, LE_CSR0);
531 writereg(
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/drivers/video/
H A Dgxt4500.c138 #define writereg(par, reg, val) writel((val), (par)->regs + (reg)) macro
387 writereg(par, DTG_CONTROL, ctrlreg);
399 writereg(par, PLL_C, tmp);
400 writereg(par, PLL_M, mdivtab[par->pll_m - 1]);
401 writereg(par, PLL_N, ndivtab[par->pll_n - 2]);
405 writereg(par, PLL_POSTDIV, tmp | 0x9);
408 writereg(par, PLL_POSTDIV, tmp);
412 writereg(par, CURSOR_MODE, CURSOR_MODE_OFF);
415 writereg(par, CTRL_REG0, CR0_RASTER_RESET | (CR0_RASTER_RESET << 16));
417 writereg(pa
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