/arch/sh/include/asm/ |
H A D | syscalls_64.h | 12 asmlinkage int sys_fork(unsigned long r2, unsigned long r3, 20 asmlinkage int sys_vfork(unsigned long r2, unsigned long r3,
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/arch/unicore32/lib/ |
H A D | copy_template.S | 63 sub.a r2, r2, #4 70 1: sub.a r2, r2, #(28) 76 sub.a r2, r2, #32 80 5: and.a ip, r2, #28 107 8: mov.a r2, r2 << #31 124 sub.a r2, r [all...] |
H A D | strncpy_from_user.S | 21 * r0 = dst, r1 = src, r2 = byte length 27 1: sub.a r2, r2, #1
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H A D | copy_from_user.S | 79 stm.w (r0, r2, r3), [sp-] 99 ldm.w (r1, r2), [sp]+ 101 rsub r2, r3, r2 102 stw r2, [sp]
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/arch/arm/boot/compressed/ |
H A D | head-xscale.S | 21 bic r2, pc, #0x1f 22 add r3, r2, #0x10000 @ 64 kb is quite enough... 23 1: ldr r0, [r2], #32 24 teq r2, r3
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/arch/arm/mach-prima2/ |
H A D | sleep.S | 43 ldr r2, [r5, #DENALI_CTL_22_OFF] 44 orr r2, r2, #0x1 49 str r2, [r5, #DENALI_CTL_22_OFF]
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/arch/arm/mm/ |
H A D | cache-v6.S | 208 ldrb r2, [r0] @ read for ownership 209 strb r2, [r0] @ write for ownership 220 ldrneb r2, [r1, #-1] @ read for ownership 221 strneb r2, [r1, #-1] @ write for ownership 238 ldrlo r2, [r0] @ read for ownership 239 strlo r2, [r0] @ write for ownership 255 ldr r2, [r0] @ read for ownership 276 sub r2, r1, r0 277 cmp r2, #CONFIG_CACHE_FLUSH_RANGE_LIMIT 281 ldrb r2, [r [all...] |
H A D | tlb-v4wb.S | 33 vma_vm_mm ip, r2 37 vma_vm_flags r2, r2 39 tst r2, #VM_EXEC
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H A D | tlb-v4wbi.S | 32 vma_vm_mm ip, r2 38 vma_vm_flags r2, r2 41 1: tst r2, #VM_EXEC
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/arch/cris/include/arch-v10/arch/ |
H A D | user.h | 10 unsigned long r2; member in struct:user_regs_struct
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/arch/cris/include/arch-v32/arch/ |
H A D | user.h | 9 unsigned long r2; member in struct:user_regs_struct
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/arch/tile/kernel/ |
H A D | entry.S | 58 { move r2, lr; lnk r1 } 65 { move r2, lr; lnk r1 } 72 * Reset our stack to r1/r2 (sp and ksp0+cpu respectively), then 79 mtspr SPR_SYSTEM_SAVE_K_0, r2 104 IRQ_ENABLE(r2, r3) /* unmask, but still with ICS set */
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/arch/arm/lib/ |
H A D | copy_page.S | 31 mov r2, #COPY_COUNT @ 1 40 subs r2, r2, #1 @ 1
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/arch/sh/lib/ |
H A D | udiv_qrnnd.S | 41 /* r0: rn r1: qn */ /* r0: n1 r4: n0 r5: d r6: d1 */ /* r2: __m */ 59 sts macl,r2 60 cmp/hs r2,r0 61 sub r2,r0
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/arch/ia64/kernel/ |
H A D | mca_asm.S | 62 GET_THIS_PADDR(r2, ia64_cpu_info) // load phys addr of cpu_info into r2 64 addl r17=O(PTCE_STRIDE),r2 65 addl r2=O(PTCE_BASE),r2 67 ld8 r18=[r2],(O(PTCE_COUNT)-O(PTCE_BASE));; // r18=ptce_base 68 ld4 r19=[r2],4 // r19=ptce_count[0] 71 ld4 r20=[r2] // r20=ptce_count[1] 110 GET_THIS_PADDR(r2, ia64_mca_pal_base) 112 ld8 r16=[r2] [all...] |
H A D | fsys.S | 200 // r2,r3 = temp r4-r7 preserved 240 add r2 = TI_FLAGS+IA64_TASK_SIZE,r16 245 ld4 r2 = [r2] // process work pending flags 251 and r2 = TIF_ALLWORK_MASK,r2 256 cmp.ne p6, p0 = 0, r2 // Fallback if work is scheduled 267 ld4 r2 = [r29] // itc_jitter value 276 (p8) cmp.ne p13,p0 = r2,r0 // need itc_jitter compensation, set p13 282 MOV_FROM_ITC(p8, p6, r2, r1 [all...] |
H A D | minstate.h | 33 * r2 = points to &pt_regs.r16 140 .mem.offset 0,0; st8.spill [r16]=r2,16; \ 143 adds r2=IA64_PT_REGS_R16_OFFSET,r1; \ 157 * r2: points to &pt_regs.r16 167 .mem.offset 0,0; st8.spill [r2]=r16,16; \ 170 .mem.offset 0,0; st8.spill [r2]=r18,16; \ 173 .mem.offset 0,0; st8.spill [r2]=r20,16; \ 177 .mem.offset 0,0; st8.spill [r2]=r22,16; \ 181 .mem.offset 0,0; st8.spill [r2]=r24,16; \ 184 .mem.offset 0,0; st8.spill [r2] [all...] |
H A D | relocate_kernel.S | 28 mov r2=ip 36 dep r2=0,r2,61,3 //to physical address 39 add r3=1f-.reloc_entry, r2 43 add sp=(memory_stack_end - 16 - .reloc_entry),r2 44 add r8=(register_stack - .reloc_entry),r2 64 GET_THIS_PADDR(r2, ia64_cpu_info) // load phys addr of cpu_info into r2 66 addl r17=O(PTCE_STRIDE),r2 67 addl r2 [all...] |
/arch/ia64/kvm/ |
H A D | vmm_ivt.S | 92 adds r3=8,r2 // set up second base pointer 246 adds r3=8,r2 // set up second base pointer 341 .mem.offset 0,0; st8.spill [r16]=r2,16 343 adds r2=VMM_PT_REGS_R16_OFFSET,r1 361 adds r3=8,r2 // set up second base pointer for SAVE_REST 364 .mem.offset 0,0; st8.spill [r2]=r16,16 367 .mem.offset 0,0; st8.spill [r2]=r18,16 370 .mem.offset 0,0; st8.spill [r2]=r20,16 374 .mem.offset 0,0; st8.spill [r2]=r22,16 378 .mem.offset 0,0; st8.spill [r2] [all...] |
/arch/arm/common/ |
H A D | fiq_glue.S | 67 mov r2, sp 69 stmfd sp!, {r2, ip, lr} 72 ldmfd sp, {r2, ip, lr} 73 mov sp, r2 106 mov sp, r2
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/arch/arm/mach-tegra/ |
H A D | headsmp.S | 40 and r2, r1, r0, lsr #13 45 add r2, r2, #1 @ NumSets 52 1: sub r2, r2, #1 @ NumSets-- 56 mov r6, r2, lsl r0 60 cmp r2, #0 172 moveq r2, #FLOW_CTRL_CPU0_CSR 174 addne r2, r1, #(FLOW_CTRL_CPU1_CSR-8) 179 ldr r0, [r6, +r2] [all...] |
/arch/parisc/math-emu/ |
H A D | fpudispatch.c | 290 u_int r1,r2,t; /* operand register offsets */ local 531 r2 = extru(ir, fpr2pos, 5) * sizeof(double)/sizeof(u_int); 532 if (r2 == 0) 533 r2 = fpzeroreg; 559 &fpregs[r2],extru(ir,fptpos,5), 566 &fpregs[r2],extru(ir,fptpos,5), 590 &fpregs[r2],extru(ir,fptpos,5), 597 &fpregs[r2],extru(ir,fptpos,5), 628 r2 = extru(ir,fpr2pos,5) * sizeof(double)/sizeof(u_int); 629 if (r2 709 u_int r1,r2,t; /* operand register offsets */ local [all...] |
/arch/sh/kernel/cpu/sh3/ |
H A D | swsusp.S | 18 #define k2 r2 36 mov.l @(PBE_ADDRESS, r4), r2 44 mov.l @r2+,r1 /* 16n+0 */ 47 mov.l @r2+,r1 /* 16n+4 */ 50 mov.l @r2+,r1 /* 16n+8 */ 53 mov.l @r2+,r1 /* 16n+12 */ 74 mov.l @r15+, r2 98 mov r15, r2 ! save sp in r2 123 mov r2, r1 [all...] |
/arch/sh/lib64/ |
H A D | strcpy.S | 28 addi r2, 8, r0 34 sub r2, r23, r0 35 sub r3, r2, r21 39 ori r2,-8,r22 46 ldlo.q r2, 0, r9 50 stlo.q r2, 0, r9 59 stlo.q r2, 0, r4
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H A D | copy_user_memcpy.S | 75 add r2,r4,r5 83 stlo.l r2, 0, r0 104 st.b r2,0,r0 108 stlo.q r2, 0, r0 116 nop ! ld.b r2,0,r63 ! TAKum03020 118 st.b r2,0,r0 121 st.b r2,1,r1 129 sthi.l r2, 3, r0 138 sthi.q r2, 7, r0 146 sthi.q r2, [all...] |