Searched refs:r2 (Results 226 - 250 of 421) sorted by relevance

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/arch/arm/kernel/
H A Dhead-common.S35 /* Determine validity of the r2 atags pointer. The heuristic requires
43 * r2 either valid atags pointer, valid dtb pointer, or zero
47 tst r2, #0x3 @ aligned?
50 ldr r5, [r2, #0]
59 ldr r5, [r2, #4]
66 1: mov r2, #0
76 * r2 = atags/dtb pointer
100 str r2, [r6] @ Save atags pointer
/arch/arm/mm/
H A Dcache-fa.S66 mov r2, #VM_EXEC
69 tst r2, #VM_EXEC
92 1: tst r2, #VM_EXEC
98 tst r2, #VM_EXEC
227 cmp r2, #DMA_TO_DEVICE
H A Dproc-xsc3.S171 mov r2, #VM_EXEC
175 tst r2, #VM_EXEC
198 1: tst r2, #VM_EXEC
204 tst r2, #VM_EXEC
324 cmp r2, #DMA_TO_DEVICE
361 clean_d_cache r1, r2
401 orrne r2, r2, #PTE_EXT_COHERENT @ interlock: mask in coherent bit
402 bic r2, r2, #
[all...]
/arch/powerpc/kvm/
H A Dbook3s_segment.S31 tophys(reg, r2); \
85 PPC_STL r2, HSTATE_HOST_R2(r3)
137 PPC_LL r2, SVCPU_R2(r3)
182 PPC_STL r2, SVCPU_R2(r13)
195 PPC_LL r2, HSTATE_HOST_R2(r13)
/arch/s390/lib/
H A Dstring.c262 register unsigned long r2 asm("2") = (unsigned long) s1;
272 : "=&d" (cc), "+a" (r2), "+a" (r3),
314 register unsigned long r2 asm("2") = (unsigned long) cs;
324 : "=&d" (ret), "+a" (r2), "+a" (r3), "+a" (r4), "+a" (r5)
327 ret = *(char *) r2 - *(char *) r4;
/arch/openrisc/kernel/
H A Dentry.S58 l.lwz r2,PT_GPR2(r1) ;\
96 l.sw PT_GPR2(r1),r2 ;\
135 l.sw PT_GPR2(r1),r2 ;\
315 // l.mfspr r2,r0,SPR_EEAR_BASE /* Load the efective addres */
316 l.addi r2,r4,0
383 lhs: l.lbs r5,0(r2)
385 l.lbz r6,1(r2)
393 lhz: l.lbz r5,0(r2)
395 l.lbz r6,1(r2)
403 lws: l.lbs r5,0(r2)
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H A Dhead.S78 #define EXCEPTION_STORE_GPR2 l.sw 0x64(r0),r2
79 #define EXCEPTION_LOAD_GPR2 l.lwz r2,0x64(r0)
455 CLEAR_GPR(r2)
591 CLEAR_GPR(r2)
828 l.and r2, r3, r6 // r2 <- r3 % NSETS_MASK
835 l.mtspr r2,r5,SPR_DTLBMR_BASE(0) // set DTLBMR
849 l.mtspr r2,r5,SPR_DTLBTR_BASE(0) // set DTLBTR
915 l.and r2, r3, r6 // r2 <
[all...]
/arch/powerpc/kernel/
H A Dhead_fsl_booke.S139 li r2,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
141 oris r2,r2,MAS4_TLBSELD(1)@h
143 mtspr SPRN_MAS4, r2
147 mfspr r2,SPRN_HID0
148 oris r2,r2,HID0_DOZE@h
149 mtspr SPRN_HID0, r2
157 lis r2,DBCR0_IDM@h
158 mtspr SPRN_DBCR0,r2
[all...]
/arch/tile/kernel/
H A Dintvec_64.S246 st sp, r2
302 mfspr r2, SPR_SYSTEM_SAVE_K_3 /* address of page fault */
306 mfspr r2, ILL_TRANS_REASON
309 mfspr r2, SPR_SYSTEM_SAVE_K_2 /* double fault info from HV */
312 mfspr r2, GPV_REASON
315 mfspr r2, PERF_COUNT_STS
319 mfspr r2, AUX_PERF_COUNT_STS
562 { move r32, r2; move r33, r3 }
567 { move r2, r32; move r3, r33 }
786 pop_reg_zero lr, r2, s
[all...]
H A Dintvec_32.S246 sw sp, r2
308 mfspr r2, SPR_SYSTEM_SAVE_K_3 /* address of page fault */
313 mfspr r2, SPR_SYSTEM_SAVE_K_2 /* double fault info from HV */
319 mfspr r2, GPV_REASON
325 mfspr r2, PERF_COUNT_STS
332 mfspr r2, AUX_PERF_COUNT_STS
601 { move r32, r2; move r33, r3 }
606 { move r2, r32; move r3, r33 }
980 pop_reg_zero r30, r2, sp, PTREGS_OFFSET_PC - PTREGS_OFFSET_REG(30)
1065 pop_reg r2
[all...]
/arch/arm/mach-pxa/
H A Dstandby.S24 mov r2, #PWRMODE_STANDBY
30 1: mcr p14, 0, r2, c7, c0, 0 @ put the system into Standby
62 ldr r2, [r1] @ Dummy read PXA3_MDCNFG
/arch/arm/mach-sa1100/
H A Dsleep.S67 * r2 = &MSC2
83 ldr r2, =MSC2
93 ldr r5, [r2]
122 str r5, [r2]
/arch/cris/boot/rescue/
H A Dhead_v10.S182 movu.w [$r3+], $r2 ; ptable length
183 move.d $r2, $r8 ; save for later, length of total ptable
187 jsr checksum ; r1 source, r2 length, returns in r0
201 move.d [$r3+], $r2 ; partition length
202 sub.d $r8, $r2 ; minus the ptable length
208 move.d [$r3+], $r2 ; partition length
263 move.b CONFIG_ETRAX_DEF_R_PORT_PA_DATA, $r2
266 move.b CONFIG_ETRAX_DEF_R_PORT_PB_DATA, $r2
272 or.d $r0, $r2 ; set bit
276 and.d $r0, $r2
[all...]
/arch/sh/lib/
H A Dcopy_page.S20 * r0, r1, r2, r3, r4, r5, r6, r7 --- scratch
40 mov.l @r11+,r2
57 mov.l r2,@-r10
113 mov r6, r2
115 shlr2 r2
192 EX( mov.l @r5+,r2 )
206 EX( mov.l r2,@(8,r4) )
233 mov r2,r7
239 and r0,r2
306 tst r2,r
[all...]
H A Dmemset-sh4.S60 mov r6,r2
62 shld r0,r2 ! number of loops
75 dt r2
H A Dmovmem.S207 mov.l @r5+,r2
210 mov.l r2,@(8,r4)
220 mov.l @r5+,r2
226 mov.l r2,@(8,r4)
234 mov.l @(8,r5),r2
238 mov.l r2,@(8,r4)
/arch/tile/mm/
H A Dmigrate_32.S54 * r2 low word of PTE to use for context access (moved to r_access_lo)
63 #define r_access_lo_in r2
137 auli r2, zero, ha16(HV_FLUSH_EVICT_L2) /* cache_control */
161 move r2, r_access_lo
/arch/unicore32/mm/
H A Dproc-ucv2.S124 sub r2, r0, #PAGE_OFFSET
125 movc p0.c5, r2, #11 @ Dcache clean line
131 @dcacheline_flush r0, r2, ip
/arch/mips/mm/
H A Dtlbex.c48 int r2; member in struct:work_registers
276 r.r2 = K1;
315 r.r2 = 1;
1799 build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */
1801 build_get_pgde32(p, wr.r1, wr.r2); /* get pgd in ptr */
1810 build_is_huge_pte(p, r, wr.r1, wr.r2, label_tlb_huge_update);
1814 UASM_i_LW(p, wr.r2, 0, wr.r2);
1817 UASM_i_ADDU(p, wr.r2, wr.r2, w
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/arch/arm/mach-omap1/
H A Dsleep.S108 bic r2, r9, #0x1000
109 mcr p15, 0, r2, c1, c0, 0
116 mov r2, #0
117 mcr p15, 0, r2, c7, c0, 4 @ wait for interrupt
199 mov r2, #0
200 mcr p15, 0, r2, c7, c0, 4 @ wait for interrupt
265 mov r2, #0
266 mcr p15, 0, r2, c7, c0, 4 @ wait for interrupt
/arch/ia64/lib/
H A Didiv32.S44 mov r2 = 0xffdd // r2 = -34 + 65535 (fp reg format bias)
58 setf.exp f7 = r2 // f7 = 2^-34
/arch/parisc/kernel/
H A Dunwind.c371 struct pt_regs *r2; local
373 r2 = kmalloc(sizeof(struct pt_regs), GFP_ATOMIC);
374 if (!r2)
376 *r2 = *r;
377 r2->gr[30] = r->ksp;
378 r2->iaoq[0] = r->kpc;
379 unwind_frame_init(info, t, r2);
380 kfree(r2);
/arch/powerpc/include/asm/
H A Dkvm_para.h129 static inline long kvm_hypercall0_1(unsigned int nr, unsigned long *r2) argument
136 *r2 = out[0];
/arch/arm/mach-omap2/
H A Dsram242x.S48 mov r12, r2 @ capture CS1 vs CS0
52 ldr r2, omap242x_sdi_cm_clksel2_pll @ get address of dpllout reg
54 str r3, [r2] @ go to L1-freq operation
82 str r3, [r2] @ go to L0-freq operation
146 * r0 = [PRCM_FULL | PRCM_HALF] r1 = SDRC_DLLA_CTRL value r2 = [DDR | SDR]
187 cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL
191 ldr r2, omap242x_srs_sdrc_dlla_ctrl @ addr of dlla ctrl
192 str r1, [r2] @ write out new SDRC_DLLA_CTRL
193 add r2, r2, #
[all...]
H A Dsram243x.S48 mov r12, r2 @ capture CS1 vs CS0
52 ldr r2, omap243x_sdi_cm_clksel2_pll @ get address of dpllout reg
54 str r3, [r2] @ go to L1-freq operation
82 str r3, [r2] @ go to L0-freq operation
146 * r0 = [PRCM_FULL | PRCM_HALF] r1 = SDRC_DLLA_CTRL value r2 = [DDR | SDR]
187 cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL
191 ldr r2, omap243x_srs_sdrc_dlla_ctrl @ addr of dlla ctrl
192 str r1, [r2] @ write out new SDRC_DLLA_CTRL
193 add r2, r2, #
[all...]

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