Searched refs:base (Results 126 - 150 of 1118) sorted by relevance

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/drivers/watchdog/
H A Dof_xilinx_wdt.c60 void __iomem *base; member in struct:xwdt_device
81 control_status_reg = ioread32(xdev.base + XWT_TWCSR0_OFFSET);
85 xdev.base + XWT_TWCSR0_OFFSET);
87 iowrite32(XWT_CSRX_EWDT2_MASK, xdev.base + XWT_TWCSR1_OFFSET);
96 control_status_reg = ioread32(xdev.base + XWT_TWCSR0_OFFSET);
99 xdev.base + XWT_TWCSR0_OFFSET);
101 iowrite32(0, xdev.base + XWT_TWCSR1_OFFSET);
111 control_status_reg = ioread32(xdev.base + XWT_TWCSR0_OFFSET);
113 iowrite32(control_status_reg, xdev.base + XWT_TWCSR0_OFFSET);
124 control_status_reg = ioread32(xdev.base
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/drivers/gpio/
H A Dgpio-tnetv107x.c56 unsigned gpio = chip->base + offset;
72 unsigned gpio = chip->base + offset;
86 unsigned gpio = chip->base + offset;
103 unsigned gpio = chip->base + offset;
124 unsigned gpio = chip->base + offset;
137 unsigned gpio = chip->base + offset;
152 int i, base; local
174 for (i = 0, base = 0; base < ngpio; i++, base
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/drivers/isdn/hardware/eicon/
H A Ds_pri.c50 byte __iomem *base; local
57 base = DIVA_OS_MEM_ATTACH_ADDRESS(IoAdapter);
58 TrapID = READ_DWORD(&base[0x80]);
61 dump_trap_frame(IoAdapter, &base[0x90]);
64 regs[0] = READ_DWORD(&base[MP_PROTOCOL_OFFSET + 0x70]);
65 regs[1] = READ_DWORD(&base[MP_PROTOCOL_OFFSET + 0x74]);
66 regs[2] = READ_DWORD(&base[MP_PROTOCOL_OFFSET + 0x78]);
67 regs[3] = READ_DWORD(&base[MP_PROTOCOL_OFFSET + 0x7c]);
72 DIVA_OS_MEM_DETACH_ADDRESS(IoAdapter, base);
78 memcpy_fromio(Xlog, &base[reg
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/drivers/net/ethernet/ibm/emac/
H A Dzmii.c88 struct zmii_regs __iomem *p = dev->base;
160 fer = in_be32(&dev->base->fer) & ~ZMII_FER_MDI_ALL;
161 out_be32(&dev->base->fer, fer | ZMII_FER_MDI(input));
180 ssr = in_be32(&dev->base->ssr);
189 out_be32(&dev->base->ssr, ssr);
205 out_be32(&dev->base->fer,
206 in_be32(&dev->base->fer) & ~zmii_mode_mask(dev->mode, input));
230 memcpy_fromio(regs, dev->base, sizeof(struct zmii_regs));
258 dev->base = (struct zmii_regs __iomem *)ioremap(regs.start,
260 if (dev->base
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H A Drgmii.c99 struct rgmii_regs __iomem *p = dev->base;
128 struct rgmii_regs __iomem *p = dev->base;
150 struct rgmii_regs __iomem *p = dev->base;
171 struct rgmii_regs __iomem *p = dev->base;
195 p = dev->base;
226 memcpy_fromio(regs, dev->base, sizeof(struct rgmii_regs));
254 dev->base = (struct rgmii_regs __iomem *)ioremap(regs.start,
256 if (dev->base == NULL) {
271 in_be32(&dev->base->fer), in_be32(&dev->base
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/drivers/staging/iio/
H A Diio_dummy_evgen.c33 * @base: base of irq range
40 int base; member in struct:iio_dummy_eventgen
56 evgen->enabled[d->irq - evgen->base] = false;
65 evgen->enabled[d->irq - evgen->base] = true;
76 iio_evgen->base = irq_alloc_descs(-1, 0, IIO_EVENTGEN_NO, 0);
77 if (iio_evgen->base < 0) {
78 ret = iio_evgen->base;
86 irq_set_chip(iio_evgen->base + i, &iio_evgen->chip);
87 irq_set_handler(iio_evgen->base
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/drivers/message/i2o/
H A Dpci.c71 if (c->base.virt)
72 iounmap(c->base.virt);
101 if (!c->base.phys) {
102 c->base.phys = pci_resource_start(pdev, i);
103 c->base.len = pci_resource_len(pdev, i);
112 if (c->base.len > 0x400000)
113 c->base.len = 0x400000;
115 if (c->base.len > 0x100000)
116 c->base.len = 0x100000;
140 (unsigned long)c->base
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/drivers/scsi/arm/
H A Dcumana_2.c79 void __iomem *base; member in struct:cumanascsi2_info
96 writeb(ALATCH_ENA_INT, info->base + CUMANASCSI2_ALATCH);
108 writeb(ALATCH_DIS_INT, info->base + CUMANASCSI2_ALATCH);
128 writeb(ALATCH_ENA_TERM, info->base + CUMANASCSI2_ALATCH);
131 writeb(ALATCH_DIS_TERM, info->base + CUMANASCSI2_ALATCH);
164 writeb(ALATCH_DIS_DMA, info->base + CUMANASCSI2_ALATCH);
185 writeb(alatch_dir, info->base + CUMANASCSI2_ALATCH);
188 writeb(ALATCH_ENA_DMA, info->base + CUMANASCSI2_ALATCH);
189 writeb(ALATCH_DIS_BIT32, info->base + CUMANASCSI2_ALATCH);
223 unsigned int status = readb(info->base
405 void __iomem *base; local
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/drivers/staging/vme/bridges/
H A Dvme_tsi148.c130 val = ioread32be(bridge->base + TSI148_GCSR_MBOX[i]);
151 ioread32be(bridge->base + TSI148_LCSR_EDPAU),
152 ioread32be(bridge->base + TSI148_LCSR_EDPAL),
153 ioread32be(bridge->base + TSI148_LCSR_EDPAT));
157 ioread32be(bridge->base + TSI148_LCSR_EDPXA),
158 ioread32be(bridge->base + TSI148_LCSR_EDPXS));
160 iowrite32be(TSI148_LCSR_EDPAT_EDPCL, bridge->base + TSI148_LCSR_EDPAT);
178 error_addr_high = ioread32be(bridge->base + TSI148_LCSR_VEAU);
179 error_addr_low = ioread32be(bridge->base + TSI148_LCSR_VEAL);
180 error_attrib = ioread32be(bridge->base
[all...]
/drivers/mmc/host/
H A Dimxmmc.c46 void __iomem *base; member in struct:imxmci_host
104 reg = readw(host->base + MMC_REG_STR_STP_CLK);
105 writew(reg & ~STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK);
108 reg = readw(host->base + MMC_REG_STR_STP_CLK);
110 host->base + MMC_REG_STR_STP_CLK);
113 reg = readw(host->base + MMC_REG_STATUS);
116 reg = readw(host->base + MMC_REG_STATUS);
133 reg = readw(host->base + MMC_REG_STR_STP_CLK);
134 writew(reg & ~STR_STP_CLK_STOP_CLK, host->base + MMC_REG_STR_STP_CLK);
143 reg = readw(host->base
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H A Dsdhci-pltfm.h62 int base = reg & ~0x3; local
79 clrsetbits_be32(host->ioaddr + base, 0xffff << shift, val << shift);
84 int base = reg & ~0x3; local
87 clrsetbits_be32(host->ioaddr + base , 0xff << shift, val << shift);
/drivers/base/
H A Dmap.c2 * linux/drivers/base/map.c
139 struct probe *base = kzalloc(sizeof(*base), GFP_KERNEL); local
142 if ((p == NULL) || (base == NULL)) {
144 kfree(base);
148 base->dev = 1;
149 base->range = ~0;
150 base->get = base_probe;
152 p->probes[i] = base;
/drivers/char/hw_random/
H A Datmel-rng.c26 void __iomem *base; member in struct:atmel_trng
37 if (readl(trng->base + TRNG_ISR) & 1) {
38 *data = readl(trng->base + TRNG_ODATA);
45 readl(trng->base + TRNG_ISR);
69 trng->base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
70 if (!trng->base)
81 writel(TRNG_KEY | 1, trng->base + TRNG_CR);
107 writel(TRNG_KEY, trng->base + TRNG_CR);
/drivers/gpu/drm/gma500/
H A Dmdfld_dsi_dpi.h45 struct mdfld_dsi_encoder base; member in struct:mdfld_dsi_dpi_output
55 container_of(dsi_encoder, struct mdfld_dsi_dpi_output, base)
/drivers/gpu/drm/nouveau/
H A Dnouveau_connector.h58 struct drm_connector base; member in struct:nouveau_connector
79 return container_of(con, struct nouveau_connector, base);
H A Dnouveau_crtc.h31 struct drm_crtc base; member in struct:nouveau_crtc
77 return container_of(crtc, struct nouveau_crtc, base);
82 return &crtc->base;
/drivers/ide/
H A Dbuddha.c121 static void __init buddha_setup_ports(struct ide_hw *hw, unsigned long base, argument
128 hw->io_ports.data_addr = base;
131 hw->io_ports_array[i] = base + 2 + i * 4;
212 unsigned long base, ctl, irq_port; local
215 base = buddha_board + buddha_bases[i];
216 ctl = base + BUDDHA_CONTROL;
219 base = buddha_board + xsurf_bases[i];
225 buddha_setup_ports(&hw[i], base, ctl, irq_port);
H A Ddelkin_cb.c51 unsigned long base = pci_resource_start(dev, 0); local
54 outb(0x02, base + 0x1e); /* set nIEN to block interrupts */
55 inb(base + 0x17); /* read status to clear interrupts */
59 outb(setup[i], base + i);
78 unsigned long base; local
93 base = pci_resource_start(dev, 0);
98 ide_std_init_ports(&hw, base + 0x10, base + 0x1e);
/drivers/mfd/
H A Ddavinci_voicecodec.c37 return __raw_readl(davinci_vc->base + reg);
43 __raw_writel(val, davinci_vc->base + reg);
87 davinci_vc->base = ioremap(davinci_vc->pbase, davinci_vc->base_size);
88 if (!davinci_vc->base) {
103 (dma_addr_t)(io_v2p(davinci_vc->base) + DAVINCI_VC_WFIFO);
114 (dma_addr_t)(io_v2p(davinci_vc->base) + DAVINCI_VC_RFIFO);
141 iounmap(davinci_vc->base);
160 iounmap(davinci_vc->base);
/drivers/char/tpm/
H A Dtpm_nsc.c75 *data = inb(chip->vendor.base + NSC_STATUS);
83 *data = inb(chip->vendor.base + 1);
98 status = inb(chip->vendor.base + NSC_STATUS);
100 status = inb(chip->vendor.base + NSC_DATA);
108 status = inb(chip->vendor.base + NSC_STATUS);
110 status = inb(chip->vendor.base + NSC_DATA);
136 inb(chip->vendor.base + NSC_DATA)) != NSC_COMMAND_NORMAL) {
152 *p = inb(chip->vendor.base + NSC_DATA);
160 if ((data = inb(chip->vendor.base + NSC_DATA)) != NSC_COMMAND_EOC) {
186 outb(NSC_COMMAND_CANCEL, chip->vendor.base
302 unsigned long base; local
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/drivers/gpu/drm/i915/
H A Dintel_crt.c48 struct intel_encoder base; member in struct:intel_crt
55 struct intel_crt, base);
272 struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private;
275 if (crt->base.type != INTEL_OUTPUT_ANALOG)
278 if (intel_ddc_probe(&crt->base, dev_priv->crt_ddc_pin)) {
311 struct drm_device *dev = crt->base.base.dev;
313 uint32_t pipe = to_intel_crtc(crt->base.base
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/drivers/input/keyboard/
H A Ddavinci_keyscan.c73 void __iomem *base; member in struct:davinci_ks
88 davinci_ks->base + DAVINCI_KEYSCAN_INTENA);
92 davinci_ks->base + DAVINCI_KEYSCAN_INTCLR);
96 davinci_ks->base + DAVINCI_KEYSCAN_STRBWIDTH);
98 davinci_ks->base + DAVINCI_KEYSCAN_INTERVAL);
100 davinci_ks->base + DAVINCI_KEYSCAN_CONTTIME);
117 matrix_ctrl, davinci_ks->base + DAVINCI_KEYSCAN_KEYCTRL);
134 __raw_writel(0x0, davinci_ks->base + DAVINCI_KEYSCAN_INTENA);
137 prev_status = __raw_readl(davinci_ks->base + DAVINCI_KEYSCAN_PREVSTATE);
138 new_status = __raw_readl(davinci_ks->base
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/drivers/scsi/
H A Ddtc.c146 static struct base { struct
215 void __iomem *base; local
223 base = NULL;
227 base = ioremap(addr, 0x2000);
228 if (!base)
237 base = ioremap(bases[current_base].address, 0x2000);
238 if (!base)
241 if (check_signature(base + signatures[sig].offset, signatures[sig].string, strlen(signatures[sig].string))) {
249 iounmap(base);
253 printk(KERN_DEBUG "scsi-dtc : base
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/drivers/pcmcia/
H A Drsrc_mgr.c48 unsigned int *base, unsigned int num,
53 *base = s->io_offset | (*base & 0x0fff);
47 static_find_io(struct pcmcia_socket *s, unsigned int attr, unsigned int *base, unsigned int num, unsigned int align, struct resource **parent) argument
/drivers/pci/hotplug/
H A Dcpqphp_ctrl.c428 if ((*head)->base != (*orig_head)->base)
452 split_node->base = node->base;
456 node->base += split_node->length;
510 if (node->base & (alignment - 1)) {
512 temp_dword = (node->base | (alignment-1)) + 1;
513 if ((node->length - (temp_dword - node->base)) < alignment)
516 node->length -= (temp_dword - node->base);
517 node->base
2383 u32 base; local
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